1
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
TP2424
Features
Low threshold
High input impedance
Low input capacitance
Fast switching speeds
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces ideal for TTL and CMOS
Solid state relays
Linear Amplifiers
Power Management
Analog switches
Telecom switches
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) power
transistors utilize a vertical DMOS structure and Supertex's well-
proven silicon-gate manufacturing process. This combination
produces devices with the power handling capabilities of bipolar
transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic
of all MOS structures, these devices are free from thermal
runaway and thermally induced secondary breakdown.
Supertex's vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
P-Channel Enhancement-Mode
Vertical DMOS FETs
Absolute Maximum Ratings
Drain-to-Source Voltage
BV
DSS
Drain-to-Gate Voltage
BV
DGS
Gate-to-Source Voltage
20V
Operating and Storage Temperature
-55
C to +150
C
Soldering Temperature*
300
C
*
Distance of 1.6 mm from case for 10 seconds.
Low Threshold
Ordering Information
Order Number / Package
BV
DSS
/
R
DS(ON)
V
GS(th)
I
D(ON)
BV
DGS
(max)
(max)
(min)
TO-243AA*
Die
-240V
8.0
-2.4V
-800mA
TP2424N8
TP2424ND
*
Same as SOT-89. Product supplied on 2000 piece carrier tape reels.
Package Option
Note: See Package Outline section for dimensions.
TO-243AA
(SOT-89)
G
D
S
D
Product marking for TO-243AA:
TP4C
where
= 2-week alpha date code
2
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
11/12/01
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
TP2424
Switching Waveforms and Test Circuit
90%
10%
90%
90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
0V
V
DD
R
gen
0V
-10V
Thermal Characteristics
Package
I
D
(continuous)*
I
D
(pulsed)
Power Dissipation
jc
ja
I
DR
*
I
DRM
@ T
A
= 25
C
C/W
C/W
TO-243AA
-316mA
-1.9A
1.6W
15
78
-316mA
-1.9A
* I
D
(continuous) is limited by max rated T
j
.
Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P
D
increase possible on ceramic substrate.
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
BV
DSS
Drain-to-Source
-240
V
V
GS
= 0V, I
D
= -250
A
Breakdown Voltage
V
GS(th)
Gate Threshold Voltage
-1.0
-2.4
V
V
GS
= V
DS
, I
D
= -1.0mA
V
GS(th)
Change in V
GS(th)
with Temperature
4.5
mV/
C
V
GS
= V
DS
, I
D
= -1.0mA
I
GSS
Gate Body Leakage
-100
nA
V
GS
=
20V, V
DS
= 0V
I
DSS
Zero Gate Voltage Drain Current
-10.0
A
V
GS
= 0V, V
DS
= Max Rating
-1.0
mA
V
GS
= 0V, V
DS
= 0.8 Max Rating
T
A
= 125
C
I
D(ON)
ON-State Drain Current
-0.3
V
GS
= -4.5V, V
DS
= -25V
-0.8
V
GS
= -10V, V
DS
= -25V
R
DS(ON)
10.0
V
GS
= -4.5V, I
D
= -150mA
8.0
V
GS
= -10V, I
D
= -500mA
R
DS(ON)
Change in R
DS(ON)
with Temperature
0.75
%/
C
V
GS
= -10V, I
D
= -500mA
G
FS
Forward Transconductance
150
m
V
DS
= -25V, I
D
= -200mA
C
ISS
Input Capacitance
200
C
OSS
Common Source Output Capacitance
100
pF
C
RSS
Reverse Transfer Capacitance
40
t
d(ON)
Turn-ON Delay Time
20
t
r
Rise Time
30
t
d(OFF)
Turn-OFF Delay Time
35
t
f
Fall Time
25
V
SD
Diode Forward Voltage Drop
-1.5
V
V
GS
= 0V, I
SD
= -500mA
t
rr
Reverse Recovery Time
300
ns
V
GS
= 0V, I
SD
= -500mA
Notes:
1.All D.C. parameters 100% tested at 25
C unless otherwise stated. (Pulse test: 300
s pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
Electrical Characteristics
(@ 25
C unless otherwise specified)
A
ns
V
DD
= -25V,
I
D
= -250mA,
R
GEN
= 25
V
GS
= 0V, V
DS
= -25V
f = 1.0 MHz
Static Drain-to-Source
ON-State Resistance
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