SN74LVC1G125 Q1
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
SGES002A - APRIL 2003 - REVISED MAY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Qualification in Accordance With
AEC-Q100
D
Qualified for Automotive Applications
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D
Available in the Texas Instruments
NanoStar
and NanoFree
Packages
D
Supports 5-V V
CC
Operation
D
Inputs Accept Voltages to 5.5 V
D
Max t
pd
of 3.7 ns at 3.3 V
D
Low Power Consumption, 10-
A Max I
CC
D
24-mA Output Drive at 3.3 V
Contact factory for details. Q100 qualification data available on
request.
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
description/ordering information
This bus buffer gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
NanoStar
and NanoFree
package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40
C to 125
C
SOT (SC-70) - DCK
Reel of 2875
1P1G125QDCKRQ1
CM_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
DCK: The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
V
CC
Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74LVC1G125 Q1
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
SGES002A - APRIL 2003 - REVISED MAY 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A
Y
OE
1
2
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3)
252
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC1G125 Q1
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
SGES002A - APRIL 2003 - REVISED MAY 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
Operating
1.65
5.5
V
VCC
Supply voltage
Data retention only
1.5
V
VCC = 1.65 V to 1.95 V
0.65
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 3 V to 3.6 V
2
V
VCC = 4.5 V to 5.5 V
0.7
VCC
VCC = 1.65 V to 1.95 V
0.35
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 3 V to 3.6 V
0.8
V
VCC = 4.5 V to 5.5 V
0.3
VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
-4
VCC = 2.3 V
-8
IOH
High-level output current
VCC = 3 V
-16
mA
IOH
High-level output current
VCC = 3 V
-24
mA
VCC = 4.5 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
8
IOL
Low-level output current
VCC = 3 V
16
mA
IOL
Low-level output current
VCC = 3 V
24
mA
VCC = 4.5 V
24
VCC = 1.8 V
0.15 V, 2.5 V
0.2 V
20
t/
v
Input transition rise or fall rate
VCC = 3.3 V
0.3 V
10
ns/V
t/
v
Input transition rise or fall rate
VCC = 5 V
0.5 V
5
ns/V
TA
Operating free-air temperature
-40
125
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVC1G125 Q1
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
SGES002A - APRIL 2003 - REVISED MAY 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = -100
m
A
1.65 V to 5.5 V
VCC-0.1
IOH = -4 mA
1.65 V
1.2
V
IOH = -8 mA
2.3 V
1.9
V
VOH
IOH = -16 mA
3 V
2.4
V
IOH = -24 mA
3 V
2.3
IOH = -24 mA
4.5 V
3.8
IOL = 100
m
A
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
V
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
3 V
0.4
V
IOL = 24 mA
3 V
0.55
IOL = 24 mA
4.5 V
0.55
II
A or OE inputs
VI = 5.5 V or GND
0 to 5.5 V
5
m
A
Ioff
VI or VO = 5.5 V
0
10
m
A
IOZ
VO = 0 to 5.5 V
3.6 V
10
m
A
ICC
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
10
m
A
ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 5.5 V
500
m
A
Ci
VI = VCC or GND
3.3 V
4
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
0.3 V
VCC = 5 V
0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tpd
A
Y
1
5.1
1
4.1
ns
ten
OE
Y
1
6
1
5
ns
tdis
OE
Y
1
5
0.5
4.2
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST
VCC = 3.3 V
VCC = 5 V
UNIT
PARAMETER
TEST
CONDITIONS
TYP
TYP
UNIT
Cpd
Power dissipation capacitance
Outputs enabled
f = 10 MHz
19
21
pF
Cpd
Power dissipation capacitance
Outputs disabled
f = 10 MHz
2
4
pF
SN74LVC1G125 Q1
SINGLE BUS BUFFER GATE
WITH 3 STATE OUTPUT
SGES002A - APRIL 2003 - REVISED MAY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V
VOH - V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VM
VI
VM
VM
3.3 V
0.3 V
5 V
0.5 V
500
500
VCC
RL
6 V
2
VCC
VLOAD
CL
50 pF
50 pF
0.3 V
0.3 V
V
3 V
VCC
VI
1.5 V
VCC/2
VM
tr/tf
2.5 ns
2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
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