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1OEAB
1OEBA
V
CC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
V
CC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
V
CC
2A8
GND
2OEAB
2OEBA
CLK
1LEAB
1LEBA
ERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
V
CC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
V
REF
2B6
GND
2B7
2B8
BIAS V
CC
2LEAB
2LEBA
OE
DESCRIPTION
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
Member of Texas Instruments' WidebusTM
Family
UBTTM Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
TI-OPCTM Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OECTM Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
Partitioned as Two 8-Bit Transceivers With
Individual Latch Timing and Output Control,
but With a Common Clock
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
The SN74GTLPH1655 is a high-drive, 16-bit UBTTM transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent,
latched, and clocked modes of data transfer. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OECTM circuitry, and TI-OPCTM circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 11
.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 19992005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION (CONTINUED)
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
GTLP is the Texas Instruments (TITM) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH1655 is given only at the preferred higher noise-margin GTLP,
but
the
user
has
the
flexibility
of
using
this
device
at
either
GTL
(V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V
CC
adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
40C to 85C
TSSOP DGG
Tape and reel
SN74GTLPH1655DGGR
GTLPH1655
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTIONAL DESCRIPTION
The SN74GTLPH1655 is a high-drive (100 mA), 16-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, or clocked modes. The device is uniquely partitioned as
two 8-bit transceivers with individual latch timing and output signals and a common clock for both transceiver
words. It can replace any of the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH1655 UBT Transceiver Replacement Functions
FUNCTION
8 BIT
9 BIT
10 BIT
16 BIT
Transceiver
'245, '623, '645
'863
'861
'16245, '16623
Buffer/driver
'241, '244, '541
'827
'16241, '16244, '16541
Latched transceiver
'543
'16543
Latch
'373, '573
'843
'841
'16373
Registered transceiver
'646, '652
'16646, '16652
Flip-flop
'374, '574
'821
'16374
SN74GTLPH1655 UBT transceiver replaces all above functions
2
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FUNCTIONAL DESCRIPTION (CONTINUED)
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables
(xOEAB and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control
byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively. Note that CLK is common to both
directions and both 8-bit words. OE also is common and disables all I/O ports simultaneously.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions
low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK
low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the
high-impedance state.
The data flow for the B-to-A direction is identical, except OEBA, LEBA, and CLK are used.
FUNCTION TABLES
XXX
FUNCTION
(1)
INPUTS
OUTPUT
MODE
B
OEAB
LEAB
CLK
A
H
X
X
X
Z
Isolation
L
L
H
X
B
0
(2)
Latched storage of A data
L
L
L
X
B
0
(3)
L
H
X
L
L
True transparent
L
H
X
H
H
L
L
L
L
Clocked storage of A data
L
L
H
H
(1)
A-to-B data flow is shown. B-to-A flow is similar, but uses OEBA, LEBA, and CLK. The condition
when OEAB and OEBA are both low at the same time is not recommended.
(2)
Output level before the indicated steady-state input conditions were established, provided that CLK
was high before LEAB went low
(3)
Output level before the indicated steady-state input conditions were established
OUTPUT ENABLE
INPUTS
OUTPUTS
OE
OEAB
OEBA
A PORT
B PORT
L
L
L
Active
Active
(1)
L
L
H
Z
Active
L
H
L
Active
Z
L
H
H
Z
Z
H
X
X
Z
Z
(1)
This condition is not recommended.
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC
OUTPUT
B-PORT
LOGIC LEVEL
NOMINAL VOLTAGE
EDGE RATE
H
V
CC
Slow
L
GND
Fast
3
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1D
C1
CLK
1D
C1
CLK
1B1
1OEAB
CLK
1LEAB
1LEBA
1OEBA
1A1
1
64
63
62
2
4
59
To Seven Other Channels
OE
33
ERC
61
V
REF
41
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
4
www.ti.com
1D
C1
CLK
1D
C1
CLK
2B1
2OEAB
CLK
2LEAB
2LEBA
2OEBA
2A1
31
64
35
34
32
17
48
To Seven Other Channels
OE
33
ERC
61
V
REF
41
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
LOGIC DIAGRAM (POSITIVE LOGIC) (CONTINUED)
5
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Absolute Maximum Ratings
(1)
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
4.6
V
BIAS V
CC
A port, ERC, and control inputs
0.5
7
V
I
Input voltage range
(2)
V
B port and V
REF
0.5
4.6
A port
0.5
7
Voltage range applied to any output
V
O
V
in the high-impedance or power-off state
(2)
B port
0.5
4.6
A port
48
I
O
Current into any output in the low state
mA
B port
200
I
O
Current into any A-port output in the high state
(3)
48
mA
Continuous current through each V
CC
or GND
100
mA
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
JA
Package thermal impedance
(4)
55
C/W
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This current flows only when the output is in the high state and V
O
> V
CC
.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
6
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Recommended Operating Conditions
(1) (2) (3) (4)
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
MIN
NOM
MAX
UNIT
V
CC
,
Supply voltage
3.15
3.3
3.45
V
BIAS V
CC
GTL
1.14
1.2
1.26
V
TT
Termination voltage
V
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
V
REF
Reference voltage
V
GTLP
0.87
1
1.1
B port
V
TT
V
I
Input voltage
V
Except B port
V
CC
5.5
B port
V
REF
+ 0.05
V
IH
High-level input voltage
ERC
V
CC
0.6
V
CC
5.5
V
Except B port and ERC
2
B port
V
REF
0.05
V
IL
Low-level input voltage
ERC
GND
0.6
V
Except B port and ERC
0.8
I
IK
Input clamp current
18
mA
I
OH
High-level output current
A port
24
mA
A port
24
I
OL
Low-level output current
mA
B port
100
t/
v
Input transition rise or fall rate
Outputs enabled
10
ns/V
t/
V
CC
Power-up ramp rate
20
s/V
T
A
Operating free-air temperature
40
85
C
(1)
All unused control and B-port inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2)
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
CC
= 3.3 V first, I/O second, and V
CC
= 3.3 V
last, because the BIAS V
CC
precharge circuitry is disabled when any V
CC
pin is connected. The control and V
REF
inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
(3)
V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.
(4)
V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when V
TT
> 0.7 V above V
REF
. If operated in the A-to-B direction, V
REF
should be set to within 0.6 V of V
TT
to minimize current
drain.
7
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Electrical Characteristics
Hot-Insertion Specifications for A Port
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
(1)
MAX
UNIT
V
IK
V
CC
= 3.15 V,
I
I
= 18 mA
1.2
V
V
CC
= 3.15 V to 3.45 V,
I
OH
= 100
A
V
CC
0.2
V
OH
A port
I
OH
= 12 mA
2.4
V
V
CC
= 3.15 V
I
OH
= 24 mA
2
V
CC
= 3.15 V to 3.45 V,
I
OL
= 100
A
0.2
A port
I
OL
= 12 mA
0.4
V
CC
= 3.15 V
I
OL
= 24 mA
0.5
V
OL
V
I
OL
= 10 mA
0.2
B port
V
CC
= 3.15 V
I
OL
= 64 mA
0.4
I
OL
= 100 mA
0.55
I
I
Control inputs
V
CC
= 3.45 V,
V
I
= 0 or 5.5 V
10
A
A port
V
O
= V
CC
10
I
OZH
(2)
V
CC
= 3.45 V
A
B port
V
O
= 1.5 V
10
I
OZL
(2)
A and B ports
V
CC
= 3.45 V,
V
O
= GND
10
A
I
BHL
(3)
A port
V
CC
= 3.15 V,
V
I
= 0.8 V
75
A
I
BHH
(4)
A port
V
CC
= 3.15 V,
V
I
= 2 V
75
A
I
BHLO
(5)
A port
V
CC
= 3.45 V,
V
I
= 0 to V
CC
500
A
I
BHHO
(6)
A port
V
CC
= 3.45 V,
V
I
= 0 to V
CC
500
A
Outputs high
40
V
CC
= 3.45 V, I
O
= 0,
I
CC
A or B port
V
I
(A-port or control input) = V
CC
or GND,
Outputs low
40
mA
V
I
(B port) = V
TT
or GND
Outputs disabled
40
V
CC
= 3.45 V, One A-port or control input at V
CC
0.6 V,
I
CC
(7)
1.5
mA
Other A-port or control inputs at V
CC
or GND
C
i
Control inputs
V
I
= 3.15 V or 0
4.5
6.5
pF
A port
V
O
= 3.15 V or 0
6.5
7.5
C
io
pF
B port
V
O
= 1.5 V or 0
8.5
10.5
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25C.
(2)
For I/O ports, the parameters I
OZH
and I
OZL
include the input leakage current.
(3)
The bus-hold circuit can sink at least the minimum low sustaining current at V
IL
max. I
BHL
should be measured after lowering V
IN
to GND
and then raising it to V
IL
max.
(4)
The bus-hold circuit can source at least the minimum high sustaining current at V
IH
min. I
BHH
should be measured after raising V
IN
to V
CC
and then lowering it to V
IH
min.
(5)
An external driver must source at least I
BHLO
to switch this node from low to high.
(6)
An external driver must sink at least I
BHHO
to switch this node from high to low.
(7)
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
off
V
CC
= 0,
BIAS V
CC
= 0,
V
I
or V
O
= 0 to 5.5 V
10
A
I
OZPU
V
CC
= 0 to 1.5 V,
V
O
= 0.5 V to 3 V,
OE = 0
30
A
I
OZPD
V
CC
= 1.5 V to 0,
V
O
= 0.5 V to 3 V,
OE = 0
30
A
8
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Live-Insertion Specifications for B Port
Timing Requirements
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
off
V
CC
= 0,
BIAS V
CC
= 0,
V
I
or V
O
= 0 to 1.5 V
10
A
I
OZPU
V
CC
= 0 to 1.5 V,
BIAS V
CC
= 0,
V
O
= 0.5 V to 1.5 V, OE = 0
30
A
I
OZPD
V
CC
= 1.5 V to 0,
BIAS V
CC
= 0,
V
O
= 0.5 V to 1.5 V, OE = 0
30
A
V
CC
= 0 to 3.15 V
5
mA
I
CC
(BIAS V
CC
)
BIAS V
CC
= 3.15 V to 3.45 V,
V
O
(B port) = 0 to 1.5 V
V
CC
= 3.15 V to 3.45 V
10
A
V
O
V
CC
= 0,
BIAS V
CC
= 3.3 V
I
O
= 0
0.95
1.05
V
I
O
V
CC
= 0,
BIAS V
CC
= 3.15 V to 3.45 V,
V
O
(B port) = 0.6 V
1
A
over recommended ranges of supply voltage and operating free-air temperature,
V
TT
= 1.5 V and V
REF
= 1 V for GTLP (unless otherwise noted)
MIN
MAX
UNIT
f
clock
Clock frequency
175
MHz
LEAB or LEBA high
3
t
w
Pulse duration
ns
CLK high or low
3
A before CLK
3
B before CLK
3
t
su
Setup time
ns
A before LEAB
, CLK = don't care
2.5
B before LEBA
, CLK = don't care
2.5
A after CLK
0.5
B after CLK
0.5
t
h
Hold time
ns
A after LEAB
, CLK = don't care
0.5
B after LEBA
, CLK = don't care
0.5
9
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Switching Characteristics
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
over recommended ranges of supply voltage and operating free-air temperature,
V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1)
FROM
TO
PARAMETER
EDGE RATE
(1)
MIN TYP
(2)
MAX
UNIT
(INPUT)
(OUTPUT)
f
max
175
MHz
t
PLH
3.5
7.7
A
B
Slow
ns
t
PHL
2.4
6.3
t
PLH
2
6.3
A
B
Fast
ns
t
PHL
2
5.9
t
PLH
3.5
7.8
LEAB
B
Slow
ns
t
PHL
2.7
6.4
t
PLH
2
6.4
LEAB
B
Fast
ns
t
PHL
2
6
t
PLH
4.7
8
CLK
B
Slow
ns
t
PHL
2.7
6.4
t
PLH
3.6
6.8
CLK
B
Fast
ns
t
PHL
2
6.1
t
en
3.5
7.3
OE
B
Slow
ns
t
dis
3.5
7
t
en
2
6
OE
B
Fast
ns
t
dis
2
6.6
t
en
3.5
7.4
OEAB
B
Slow
ns
t
dis
3.5
7
t
en
2
6.1
OEAB
B
Fast
ns
t
dis
2
6.3
Slow
2.6
t
r
Rise time, B outputs (20% to 80%)
ns
Fast
1.5
Slow
3
t
f
Fall time, B outputs (80% to 20%)
ns
Fast
2.2
t
PLH
1.5
5.5
B
A
ns
t
PHL
1.5
5.5
t
PLH
1.3
5.2
LEBA
A
ns
t
PHL
1
5
t
PLH
1.2
6.3
CLK
A
ns
t
PHL
1
5
t
en
1.5
5.6
OE
A
ns
t
dis
1.5
6.1
t
en
1.2
5.4
OEBA
A
ns
t
dis
2
6.1
(1)
Slow (ERC = V
CC
) and Fast (ERC = GND)
(2)
All typical values are at V
CC
= 3.3 V, T
A
= 25C.
10
www.ti.com
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
Open
GND
500
500
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
6 V
GND
t
PLH
t
PHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
V
OL
+ 0.3 V
V
OH
- 0.3 V
0 V
3 V
0 V
t
w
Input
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(V
M
= 1.5 V for A port and 1 V for B port)
(V
OH
= 3 V for A port and 1.5 V for B port)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
Input
1.5 V
Test
Point
C
L
= 30 pF
(see Note A)
From Output
Under Test
12.5
LOAD CIRCUIT FOR B OUTPUTS
0 V
V
OH
V
OL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2 ns, t
f
2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
t
PLH
t
PHL
V
OH
0 V
V
M
V
M
Data
Input
3 V
0 V
t
su
t
h
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
1 V
1 V
1 V
1 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
Figure 1. Load Circuits and Voltage Waveforms
11
www.ti.com
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
Drvr
1.5 V
0.25"
1"
1"
1"
1.5 V
1"
1"
1"
0.25"
Rcvr
Rcvr
Rcvr
Slot 1
Slot 2
Slot 19
Slot 20
Conn.
Conn.
Conn.
Conn.
Z
O
= 50
22
22
From Output
Under Test
Test
Point
1.5 V
C
L
= 18 pF
11
L
L
= 14 nH
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
this typical backplane. See www.ti.com/sc/gtlp for more information.
Figure 2. High-Drive Test Backplane
Figure 3. High-Drive RLC Network
12
www.ti.com
Switching Characteristics
SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C OCTOBER 1999 REVISED MAY 2005
over recommended ranges of supply voltage and operating free-air temperature,
V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see
Figure 3
)
FROM
TO
PARAMETER
EDGE RATE
(1)
TYP
(2)
UNIT
(INPUT)
(OUTPUT)
t
PLH
5
A
B
Slow
ns
t
PHL
5
t
PLH
3.8
A
B
Fast
ns
t
PHL
3.8
t
PLH
4.9
LEAB
B
Slow
ns
t
PHL
4.9
t
PLH
3.9
LEAB
B
Fast
ns
t
PHL
3.9
t
PLH
4.8
CLK
B
Slow
ns
t
PHL
4.8
t
PLH
3.7
CLK
B
Fast
ns
t
PHL
3.7
t
en
4.9
OEAB or OE
B
Slow
ns
t
dis
4.7
t
en
3.5
OEAB or OE
B
Fast
ns
t
dis
4.1
Slow
2
t
r
Rise time, B outputs (20% to 80%)
ns
Fast
1.2
Slow
2.5
t
f
Fall time, B outputs (80% to 20%)
ns
Fast
1.8
(1)
Slow (ERC = V
CC
) and Fast (ERC = GND)
(2)
All typical values are at V
CC
= 3.3 V, T
A
= 25C. All values are derived from TI-SPICE models.
13
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74GTLPH1655DGGRE4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLPH1655DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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