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FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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1DIR
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
DESCRIPTION/ORDERING INFORMATION
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B AUGUST 2002 REVISED APRIL 2005
Member of the Texas Instruments WidebusTM
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
In Transparent Mode, Max t
pd
of 5.2 ns
at 3.3 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74LVC16646A can be used as two 8-bit transceivers or one 16-bit transceiver. The device consists of
bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74LVC16646ADL
SSOP DL
LVC16646A
Tape and reel
SN74LVC16646ADLR
40C to 85C
TSSOP DGG
Tape and reel
SN74LVC16646ADGGR
LVC16646A
TVSOP DGV
Tape and reel
SN74LVC16646ADGVR
LD646A
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20022005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B AUGUST 2002 REVISED APRIL 2005
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input.
Figure 1
illustrates the four fundamental bus-management functions that can be performed with
the SN74LVC16646A.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and
SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control
eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and
real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data
can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O
(1)
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1-A8
B1-B8
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
(1)
X
X
X
X
X
Unspecified
Input
Store B, A unspecified
(1)
H
X
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
(1)
The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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L
DIR
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
L
DIR
H
CLKAB
X
CLKBA
X
SAB
L
SBA
X
X
DIR
X
CLKAB CLKBA
X
SAB
X
SBA
X
L
DIR
L
CLKAB
X
CLKBA
H or L
SAB
X
SBA
H
X
H
X
X
X
X
X
X
X
L
H
H or L
X
H
X
BUS B
BUS
A
BUS B
BUS
A
BUS B
BUS
A
BUS B
BUS
A
OE
OE
OE
OE
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B AUGUST 2002 REVISED APRIL 2005
Figure 1. Bus-Management Functions
3
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1A1
1B1
1D
C1
1D
C1
One of Eight Channels
1SAB
1CLKAB
1SBA
1CLKBA
1DIR
1OE
To Seven Other Channels
2A1
2B1
1D
C1
1D
C1
One of Eight Channels
2SAB
2CLKAB
2SBA
2CLKBA
2DIR
2OE
To Seven Other Channels
56
1
55
54
2
3
5
29
28
30
31
27
26
15
52
42
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B AUGUST 2002 REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
4
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74LVC16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES408B AUGUST 2002 REVISED APRIL 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
6.5
V
V
I
Input voltage range
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high or low state
(2) (3)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
50
mA
Continuous current through each V
CC
or GND
100
mA
DGG package
64
JA
Package thermal impedance
(4)
DGV package
48
C/W
DL package
56
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of V
CC
is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
Operating
1.65
3.6
V
CC
Supply voltage
V
Data retention only
1.5
V
CC
= 1.65 V to 1.95 V
0.65 V
CC
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V
1.7
V
V
CC
= 2.7 V to 3.6 V
2
V
CC
= 1.65 V to 1.95 V
0.35 V
CC
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V
0.7
V
V
CC
= 2.7 V to 3.6 V
0.8
V
I
Input voltage
0
5.5
V
High or low state
0
V
CC
V
O
Output voltage
V
3-state
0
5.5
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OH
High-level output current
mA
V
CC
= 2.7 V
12
V
CC
= 3 V
24
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OL
Low-level output current
mA
V
CC
= 2.7 V
12
V
CC
= 3 V
24
t/
v
Input transition rise or fall rate
10
ns/V
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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