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FEATURES
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
6
5
4
A
GND
B
C
V
CC
Y
3
2
1
4
5
6
B
GND
A
Y
V
CC
C
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C APRIL 2003 REVISED APRIL 2005
Available in the Texas Instruments
NanoStar TM and NanoFreeTM
Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
The SN74LVC1G386 performs the Boolean function Y = A
B
C in positive logic.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(2)
NanoStarTM WCSP (DSBGA)
SN74LVC1G386YEPR
0.23-mm Large Bump YEP
Tape and reel
_ _ _C8_
NanoFreeTM WCSP (DSBGA)
SN74LVC1G386YZPR
40
C to 85
C
0.23-mm Large Bump YZP (Pb-free)
SOT (SOT-23) DBV
Tape and reel
SN74LVC1G386DBVR
CC6_
SOT (SC-70) DCK
Tape and reel
SN74LVC1G386DCKR
C8_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
C
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
L
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20032005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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A
C
B
Y
Absolute Maximum Ratings
(1)
SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C APRIL 2003 REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
6.5
V
V
I
Input voltage range
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5
6.5
V
V
O
Voltage range applied to any output in the high or low state
(2) (3)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
50
mA
Continuous current through V
CC
or GND
100
mA
DBV package
165
JA
Package thermal impedance
(4)
DCK package
259
C/W
YEP/YZP package
123
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of V
CC
is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Recommended Operating Conditions
(1)
SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C APRIL 2003 REVISED APRIL 2005
MIN
MAX
UNIT
Operating
1.65
5.5
V
CC
Supply voltage
V
Data retention only
1.5
V
CC
= 1.65 V to 1.95 V
0.65
V
CC
V
CC
= 2.3 V to 2.7 V
1.7
V
IH
High-level input voltage
V
V
CC
= 3 V to 3.6 V
2
V
CC
= 4.5 V to 5.5 V
0.7
V
CC
V
CC
= 1.65 V to 1.95 V
0.35
V
CC
V
CC
= 2.3 V to 2.7 V
0.7
V
IL
Low-level input voltage
V
V
CC
= 3 V to 3.6 V
0.8
V
CC
= 4.5 V to 5.5 V
0.3
V
CC
V
I
Input voltage
0
5.5
V
V
O
Output voltage
0
V
CC
V
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OH
High-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OL
Low-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
V
CC
= 1.8 V
0.15 V, 2.5 V
0.2 V
20
t/
v
Input transition rise or fall rate
V
CC
= 3.3 V
0.3 V
10
ns/V
V
CC
= 5 V
0.5 V
5
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C APRIL 2003 REVISED APRIL 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
(1)
MAX
UNIT
I
OH
= 100
A
1.65 V to 5.5 V
V
CC
0.1
I
OH
= 4 mA
1.65 V
1.2
I
OH
= 8 mA
2.3 V
1.9
V
OH
V
I
OH
= 16 mA
2.4
3 V
I
OH
= 24 mA
2.3
I
OH
= 32 mA
4.5 V
3.8
I
OL
= 100
A
1.65 V to 5.5 V
0.1
I
OL
= 4 mA
1.65 V
0.45
I
OL
= 8 mA
2.3 V
0.3
V
OL
V
I
OL
= 16 mA
0.4
3 V
I
OL
= 24 mA
0.55
I
OL
= 32 mA
4.5 V
0.55
I
I
All inputs
V
I
= 5.5 V or GND
0 to 5.5 V
5
A
I
off
V
I
or V
O
= 5.5 V
0
10
A
I
CC
V
I
= 5.5 V or GND,
I
O
= 0
1.65 V to 5.5 V
10
A
I
CC
One input at V
CC
0.6 V,
Other inputs at V
CC
or GND
3 V to 5.5 V
500
A
C
i
V
I
= V
CC
or GND
3.3 V
3.5
pF
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25
C.
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 1)
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
FROM
TO
0.15 V
0.2 V
0.3 V
0.5 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A, B, or C
Y
3
9.4
1.3
5
0.8
4.5
0.5
3.5
ns
over recommended operating free-air temperature range, C
L
= 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
FROM
TO
0.15 V
0.2 V
0.3 V
0.5 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A, B, or C
Y
3.5
12
1.8
5.5
1.3
5
1
4
ns
T
A
= 25
C
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
C
pd
Power dissipation capacitance
f = 10 MHz
17.5
18
19
22
pF
4
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PARAMETER MEASUREMENT INFORMATION
V
M
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
R
L
R
L
Data Input
Timing Input
V
I
0 V
V
I
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
I
0 V
Input
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
LOAD
/2
0 V
V
OL
+ V
V
OH
- V
0 V
V
I
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
V
LOAD
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
I
V
M
V
M
1.8 V
0.15 V
2.5 V
0.2 V
3.3 V
0.3 V
5 V
0.5 V
1 M
1 M
1 M
1 M
V
CC
R
L
2
V
CC
2
V
CC
6 V
2
V
CC
V
LOAD
C
L
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
V
CC
V
CC
3 V
V
CC
V
I
V
CC
/2
V
CC
/2
1.5 V
V
CC
/2
V
M
t
r
/t
f
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
SN74LVC1G386
SINGLE 3-INPUT POSITIVE-XOR GATE
SCES439C APRIL 2003 REVISED APRIL 2005
Figure 1. Load Circuit and Voltage Waveforms
5
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