ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 AUGUST 1985 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
1
8-Bit Resolution
Easy Microprocessor Interface or Stand-
Alone Operation
Operates Ratiometrically or With 5-V
Reference
4- or 8-Channel Multiplexer Options With
Address Logic
Shunt Regulator Allows Operation With
High-Voltage Supplies
Input Range 0 to 5 V With Single 5-V
Supply
Remote Operation With Serial Data Link
Inputs and Outputs are Compatible With
TTL and MOS
Conversion Time of 32
s at
f
clock
= 250 kHz
Designed to Be Interchangeable With
National Semiconductor ADC0834 and
ADC0838
DEVICE
TOTAL UNADJUSTED ERROR
DEVICE
A SUFFIX
B SUFFIX
ADC0834
1 LSB
1/2 LSB
ADC0838
1 LSB
1/2 LSB
description
These devices are 8-bit successive- approxima-
tion analog-to-digital converters, each with an
input-configurable multichannel multi-
plexer and serial input/output. The serial input/
output is configured to interface with standard shift
registers or microprocessors. Detailed informa-
tion on interfacing with most popular microproces-
sors is readily available from the factory.
The ADC0834 (4-channel) and ADC0838
(8-channel) multiplexer is software configured
forsingle-ended or differential inputs as well as
pseudo-differential input assignments. The differ-
ential analog voltage input allows for common-
mode rejection or offset of the analog zero input
voltage value. In addition, the voltage reference
input can be adjusted to allow encoding any
smaller analog voltage span to the full 8 bits of
resolution.
The ADC0834AC, ADC0834BC, ADC0838AC, and ADC0838BC are characterized for operation from 0
C to
70
C. The ADC0834AI, ADC0834BI, ADC0838AI, and ADC0838BI are characterized for operation from 40
C
to 85
C.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
CS
CH0
CH1
CH2
CH3
DGTL GND
V
CC
DI
CLK
SARS
DO
REF
ANLG GND
AD0834 . . . N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGTL GND
V
CC
V +
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
ADC0838 . . . N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
CS
DI
CLK
SARS
DO
CH3
CH4
CH5
CH6
CH7
ADC0838 . . . FN PACKAGE
(TOP VIEW)
CH2
CH1
CH0
REF
SE
V
V+
COM
DGTL
GND
ANLG GND
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL
CONTROL
SLAS007 AUGUST 1985 REVISED OCT
OBER
1986
POST
OFFICE BOX 655303
DALLAS, TEXAS 75265
2
CS
Circuits
To Internal
7 V
7 V
V +
SE
Only
5-Bit Shift Register
ODD\EVEN
SELECT0
EN
MUX
Analog
START
SGL\DIF
SELECT1
Circuits
To Internals
(see Note A)
DI
CLK
CS
R
D
CLK
ADC0838
ADC0838
ADC0834
CH7
CH5
CH6
COM
CH4
CH3
CH2
CH1
CH0
Comparator
SARS
CS
R
Start
S
CLK
CLK
Delay
Time
S
R
CS
DO
CS
CS
D
CLK
R
EOC
Register
Shift
9-Bit
R
CLK
First
LSB
Bit 1
Bits 07
First
MSB
Shot
One
Latch
and
Logic
SAR
R
CS
Bits 07
REF
Decoder
and
Ladder
EN
Flip-Flop
functional block diagram
NOTE A: For the ADC0834, DI is input directly to the D input of SELECT 1; SELECT 0 is forced to a high.
VCC
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 AUGUST 1985 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
functional description
The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single-ended), to an adjacent input (differential), or to a common terminal
(pseudo-differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative
() polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer
address is shifted into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single-ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock
input, the data on DI is clocked into the multiplexer address shift register. The first logic high on the input is the
start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock
input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into
the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR Status
output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is
disabled the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. The
data output DO comes out of the high-impedance state and provides a leading low for this one clock period of
multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the
incoming analog signal. The comparator output indicates whether the analog input is greater than or less than
the resistive ladder output. As the conversion proceeds, conversion data is simultaneously output from the DO
output pin, with the most significant bit (MSB) first.
After eight clock periods, the conversion is complete and the SARS output goes low.
The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If SE is held high on
the ADC0838, the value of the least significant bit (LSB) will remain on the data line. When SE is forced low,
the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored
in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time
the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 AUGUST 1985 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
functional description (continued)
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire.
This is possible because DI is only examined during the multiplexer addressing interval and DO is still in a
high-impedance state.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
sequence of operation
15
7
Select
CH Bit 1
1
Bit
tsu
Hi-Z
SARS
Don't Care
1
7
6
2
0
1
2
6
7
MSB
LSB
LSB-First Data
MSB-First Data
Even
DIF
Odd
+Sign
SGL
Bit
Start
MSB
Max
Settling
Time
DI
DO
CS
tsu
CLK
21
20
19
18
14
13
12
1
2
3
4
5
6
10
11
tconv
Hi-Z
Hi-Z
ADC0834 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
CHANNEL NUMBER
SGL/DIF
ODD/EVEN
L
L
H
H
L
H
L
H
O
1
SELECT BIT 1
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
2
3
+
+
+
+
+
+
+
+
ADC0834
H = high level, L = low level, or + = polarity of selected input pin
ADC0834A, ADC0838A, ADC0834B, ADC0838B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS007 AUGUST 1985 REVISED OCTOBER 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
sequence of operation
SGL
Odd
Bit1
SE
LSB
MSB
LSB
7
6
5
4
3
2
1
0
1
2
6
7
MSB
Time
MUX Settling
DO
LSB-Held
LSB-First Data
MSB-First Data
SE Used to Control LSB First Data
HI-Z
HI-Z
tconv
Dont Care
7
6
5
4
3
2
1
0
1
2
6
7
MSB
LSB-First Data
MSB-First Data
MSB
Time
MUX Settling
HI-Z
DO
SE
SARS
HI-Z
SEL
SEL
+
Bit0
0
1
0
1
Even
DIF
DI
Bit
Start
CS
Addressing
MUX
tSU
tsu
CLK
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
8
7
6
5
4
3
2
1
ADC0838
Sign
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