ADS5120
SBAS247B MARCH 2002 REVISED NOVEMBER 2002
www.ti.com
DESCRIPTION
The ADS5120 is a low-power, 8-channel, 10-bit, 40MSPS
CMOS Analog-to-Digital Converter (ADC) that operates from
a single 1.8V supply, while offering 1.8V and 3.3V digital I/O
flexibility. A single-ended input clock is used for simultaneous
sampling of up to eight analog differential input channels. The
flexible duty cycle adjust circuit (DCASEL) allows the use of a
non-50% clock duty cycle. Individual standby pins allow users
the ability to power-down any number of ADCs. A sample-and-
hold stage is added in front of the ADC and a digital error
correction circuit is used to generate the final digital code.
The internal reference can be bypassed to use an external
reference to suit the accuracy and temperature drift require-
ments of the application. A 10-bit parallel bus on eight chan-
nels is provided with 3-state outputs.
The speed, resolution, and low-power of the ADS5120 makes
it ideal for applications requiring high-density signal process-
ing in low-power environments.
The ADS5120 is characterized for operation from 0
C to 70
C.
FEATURES
q
8 DIFFERENTIAL ANALOG INPUTS
q
1Vp-p DIFFERENTIAL INPUT RANGE
q
INT/EXT VOLTAGE REFERENCE
q
ANALOG/DIGITAL SUPPLY 1.8V
q
DIGITAL I/O SUPPLY 1.8V/3.3V
q
INTEGRAL NONLINEARITY:
0.8LSB
q
SIGNAL-TO-NOISE: 58dB at f
IN
= 20MHz
q
SPURIOUS-FREE DYNAMIC RANGE: 72dB at
f
IN
= 20MHz
q
794mW POWER DISSIPATION
q
INDIVIDUAL CHANNEL POWER-DOWN
q
257-LEAD, 0.8 BALL PITCH, PLASTIC
MicroSTAR BGATM (16 16mm)
Copyright 2002, Texas Instruments Incorporated
8-Channel, 10-Bit, 40MSPS, 1.8V
CMOS ANALOG-TO-DIGITAL CONVERTER
MicroSTAR BGA is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
A
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
H
DCASEL
AINA+
CLK
AINA
AINH
AINH+
IREFR
AV
DD
STBY (x8)
OE
DRV
DD
DV
DD
Internal
Reference
Circuit
CM
AGND
DRVGND
DGND
BG
PDREF REFT REFB CML
APPLICATIONS
q
PORTABLE ULTRASOUND
q
PORTABLE INSTRUMENTATION
ADS5120
2
SBAS247B
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage: AV
DD
to AGND, DV
DD
to DGND ............. 0.3V to +2.2V
DRV
DD
to DGND ..................................... 0.3V to +4.0V
AGND
to DGND ...................................... 0.3V to +0.3V
AV
DD
to DV
DD
.......................................... 2.2V to +2.2V
Reference Voltage Input Range REFT, REFB to AGND ... 0.3V to AV
DD
+ 0.3V
Analog Input Voltage Range AIN to AGND ........... 0.3V to AV
DD
+ 0.3V
Clock Input CLK to DGND ..................................... 0.3V to AV
DD
+ 0.3V
Digital Input to DGND ........................................... 0.3V to DV
DD
+ 0.3V
Digital Outputs to DRGND .................................. 0.3V to DRV
DD
+ 0.3V
Operating Temperature Range (T
J
) ................................... 0
C to +105
C
Storage Temperature Range (T
STG
) ................................. 65
C + 150
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
STBY (x8)
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
A
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
B
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
C
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
D
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
E
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
F
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
G
T&H
10-Bit
ADC
3-State
Output
Buffers
D[9:0]
H
DCASEL
AINA+
CLK
AINA
AINB
AINB+
AINC+
AINC
AIND
AIND+
AINE+
AINE
AINF
AINF+
AING+
AING
AINH
AINH+
IREFR
AV
DD
OE
DRV
DD
DV
DD
Internal
Reference
Circuit
CM
AGND
DRVGND
DGND
BG
PDREF REFT REFB CML
BLOCK DIAGRAM
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS5120
MicroSTAR BGA-257
GHK
0
C to +70
C
ADS5120CGHK
ADS5120CGHK
Tray, 90
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
ADS5120
3
SBAS247B
www.ti.com
ADS5120
DC CHARACTERISTICS
AV
DD
= DV
DD
= 1.8V, DRV
DD
= 3.3V, Clock = 40MSPS, 50% Clock Duty Cycle, 0.5dBFS Input Span, Internal Reference, and T
MIN
= 0
C, and T
MAX
= +70
C, unless
otherwise noted.
ADS5120
DC CHARACTERISTICS
AV
DD
= DV
DD
= 1.8V, DRV
DD
= 3.3V, Clock = 40MSPS, 50% Clock Duty Cycle, 0.5dBFS Input Span, Internal Reference, and T
MIN
to T
MAX
, unless otherwise noted.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (STBY A-H, PDREF, OE)
DRV
DD
= 3.3V/1.8V
High-Level Input Voltage, V
IH
V
IH
= DRV
DD
0.70 DRV
DD
V
Low-Level Input Voltage, V
IL
V
IL
= 0V
0.25 DRV
DD
V
High-Level Input Current, I
IH
1
A
Low-Level Input Current, I
IL
1
A
DIGITAL INPUTS (DCASEL)
High-Level Input Voltage, V
IH
V
IH
= DV
DD
0.70 DV
DD
V
Low-Level Input Voltage, V
IL
V
IL
= 0V
0.25 DV
DD
V
High-Level Input Current, I
IH
1
A
Low-Level Input Current, I
IL
1
A
DIGITAL OUTPUTS ( DRV
DD
= 3.3/1.8V)
High-Level Output Voltage, V
OH
I
OH
= 50
A
0.8 DRV
DD
V
Low-Level Output Voltage, V
OL
I
OL
= 50
A
0.2 DRV
DD
V
External Load Capacitance, C
L
15
pF
3-State Leakage Current, I
LEAK
OE = HIGH
1
A
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
RESOLUTION
10
Bits
DC ACCURACY
Differential Nonlinearity (DNL)
0.9
0.4
+1.0
LSB
Integral Nonlinearity (INL)
1.5
0.8
+1.5
LSB
No Missing Codes
Tested
Gain Error
External Reference
1.0
0.1
+1.0
%FSR
Offset Error
External Reference
0.2
+1.8
%FSR
Gain Temperature Coefficient
80
ppm/
C
Gain Matching
0.4
%FSR
ANALOG INPUT
Input Voltage Range (AIN+, AIN)
REFB
REFT
V
Input Voltage, Differential Full-Scale
1
Vp-p
Input Common-Mode Range
(REFT + REFB) / 2
V
Input Resistance, R
IN
f
CLK
= 40MSPS
83
k
Input Capacitance, C
IN
5
pF
INTERNAL REFERENCE VOLTAGES
Reference, Top (REFT)
1.30
1.34
1.40
V
Reference, Bottom (REFB)
0.76
0.81
0.85
V
Int Reference Temperature Coefficient
50
ppm/
C
EXTERNAL REFERENCE GENERATION
Reference, Top (REFT)
1.15
1.25
1.35
V
Reference, Bottom (REFB)
0.65
0.75
0.85
V
Input Resistance, REFR
IN
(between REFB
80
and REFT)
POWER SUPPLY
f
IN
= 3.5MHz
Operating Supply Current, I
DD
398
450
mA
Analog Operating Supply Current, IAV
DD
294
340
mA
Digital Operating Supply Current, IDV
DD
44
49
mA
Driver Operating Supply Current, IDRV
DD
C
L
= 20pF
53
60
mA
Operating Voltage
AV
DD
1.65
1.8
2.0
V
DV
DD
1.65
1.8
2.0
V
DRV
DD
1.65
1.8
3.6
V
Power-Dissipation
794
850
mW
Standby Power (STBY)
CLK Running
68
mW
CLK Stopped
60
mW
PDREF = 1, External REF, CLK Running
10
15
mW
PDREF = 1, External REF, CLK Stopped
2.5
5
mW
PSRR, Power-Supply Rejection Ratio
5%
0.8
mV/V
ADS5120
4
SBAS247B
www.ti.com
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Maximum Conversion Rate
1
40
MSPS
Clock Duty Cycle
DCASEL Enabled
30 to 70
%
Data Latency
(1)
7
Clk Cycles
Clock
to Data Valid
t
DO
(1)
8
10
ns
OE
to Outputs Enabled
t
EN
(1)
8
ns
OE
Rising to Outputs Tri-Stated
t
DIS
8
ns
Aperture Delay
1
ns
Aperture Uncertainty (Jitter)
2
ps, r ms
NOTE: (1) See Timing Diagram.
ADS5120
TARGETED AC CHARACTERISTICS
AV
DD
= DV
DD
= 1.8V, DRV
DD
= 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at 0.5dBFS Input Span, Internal voltage reference, T
MIN
= 0
C,
T
MAX
= 70
C, and typical values are at T
A
= 25
C, unless otherwise noted.
ADS5120
SWITCHING CHARACTERISTICS
AV
DD
= DV
DD
= 1.8V, DRV
DD
= 3.3V, 50% Clock Duty Cycle, CLK = 40MSPS, Analog input at 0.5dBFS Input Span, Internal voltage reference, T
MIN
= 0
C,
T
MAX
= 70
C, and Typical values are at T
A
= 25
C, unless otherwise noted.
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Signal-to-Noise Ratio
(SNR)
f
IN
= 3.5MHz
55
58
dB
f
IN
= 10MHz
55
58
dB
f
IN
= 20MHz
58
dB
Signal-to-Noise and Distortion
(SINAD)
f
IN
= 3.5MHz
55
57
dB
f
IN
= 10MHz
55
57
dB
f
IN
= 20MHz
57
dB
Effective Number of Bits
(ENOB)
f
IN
= 3.5MHz
8.8
9.2
Bits
f
IN
= 10MHz
8.8
9.2
Bits
f
IN
= 20MHz
8.8
9.2
Bits
Spurious-Free Dynamic Range
(SFDR)
f
IN
= 3.5MHz
65
73
dBc
f
IN
= 10MHz
65
72
dBc
f
IN
= 20MHz
72
dBc
2nd-Harmonic Distortion
(HD2)
f
IN
= 3.5MHz
68
79
dBc
f
IN
= 10MHz
68
80
dBc
f
IN
= 20MHz
80
dBc
3rd-Harmonic Distortion
(HD3)
f
IN
= 3.5MHz
65
76
dBc
f
IN
= 10MHz
65
78
dBc
f
IN
= 20MHz
73
dBc
2-Tone Intermod. Distortion
(IMD)
f
1
= 4.43MHz, f
2
= 4.53MHz at 6.5dB
69
dBFS
Channel-to-Channel Crosstalk
f
IN
= 10MHz, DRV
DD
= 3.3V
89
dB
Large-Signal Bandwidth
(FPBW)
300
MHz
Over-Voltage Recovery Time
(1)
20
ns
Differential Gain
(1)
1
%
Differential Phase
(1)
0.25
Degree
NOTE: (1) Assured by design.
TIMING DIAGRAM (Per ADC Channel)
Analog
Input
CLK
OE
D[9:0]
S 6
S 7
S 5
S 4
S 3
S 2
S 1
S1
S2
t
DO
t
DIS
t
EN
Sample 1
Sample 2
9
10
8
7
6
5
4
3
2
1
ADS5120
5
SBAS247B
www.ti.com
NAME
PINS
I/O
TERMINAL DESCRIPTION
AV
DD
C6, C7, E6, F1, F2, F3, F5, F6, J6, N3, P3, P5, P6, P7, R6, V6, W6
I
Analog Supply, (1.8V)
AGND
A3, A5, B5, B9, C1, C5, C9, E3, E7, F7, G1, G5, G6, H6, J1, J2, M2, N5, N6, P8,
I
Analog Ground
R1, R2, R3, R7, U1, U5, U10, V5, V10, W3, W7
AINA+
U7
I
Analog Input Channel A
AINA
V7
I
Complementary Analog Input Channel A
AINB+
W4
I
Analog Input Channel B
AINB
V4
I
Complementary Analog Input Channel B
AINC+
T1
I
Analog Input Channel C
AINC
T2
I
Complementary Analog Input Channel C
AIND+
P2
I
Analog Input Channel D
AIND
P1
I
Complementary Analog Input Channel D
AINE+
G3
I
Analog Input Channel E
AINE
G2
I
Complementary Analog Input Channel E
AINF+
D1
I
Analog Input Channel F
AINF
D2
I
Complementary Analog Input Channel F
AING+
A4
I
Analog Input Channel G
AING
B4
I
Complementary Analog Input Channel G
AINH+
B6
Analog Input Channel H
AINH
A6
I
Complementary Analog Input Channel H
CLK
W9
I
Clock Input
REFT
K3, L1, J3
I/O
Reference Top
REFB
K5, J5, L5
I/O
Reference Bottom
CML
L2, L3
O
Common-Mode Level Output
BG
K1
I/O
Bandgap Decoupling (Decouple with 1
F cap to AGND
and 100k
to AV
DD
)
IREFR
K6
I
Internal Reference Bias Current (Connect 6.19k
resistor
from this pin AGND to set internal bias amplifier current.)
DNC
W5
I
Do Not Connect
DNC
U6
I
Do Not Connect
NC
E1, E2, E5, K2, L6, M1
I
No Internal Connection
DCASEL
N2
I
Duty Cycle Adjust
DV
DD
C2, C3, C4, D3, E8, F8, H3, H5, M3, M5, R8, T3, U3, U4, U8, V3, P13, R13
I
Digital Supply (1.8V)
P17, L15, J14, F17, F12, E12
DGND
A2, A7, B1, B2, B3, B7, B13, C13, G15, H1, H2, H17, L17, M6, N1, N15, U2, U13,
I
Digital Ground
U14, V1, V2, V8, W2, W8
PDREF
V9
I
Power-Down Ref: 0 = internal reference, 1 = external
reference. In external reference mode connect REFT to
BG pin.
STBY A
W10
I
Power-Down Channel A
STBY B
P9
I
Power-Down Channel B
STBY C
R9
I
Power-Down Channel C
STBY D
U9
I
Power-Down Channel D
STBY E
C8
I
Power-Down Channel E
STBY F
B8
I
Power-Down Channel F
STBY G
A8
I
Power-Down Channel G
STBY H
A9
I
Power-Down Channel H
OE
P10
I
Enable all Digital Outputs, Ch A-H. OE: 0 = Outputs
Enable. OE: 1 = Outputs disabled (3-State).
DRV
DD
B17, C16, D17, E9, E10, E11, E17, F9, H14, H15, K17, L14, N14, P12, P14, P15
I
Driver Digital Supply (1.8V or 3.3V)
R10, R12, R14
I
DRGND
E13, F10, F11, F13, F14, F15, G14, G17, M14, M15, M17, N17, U11, U12, U15, U16
I
Driver Digital Ground
PIN DESCRIPTIONS
19
14,40 TYP
17
16
13
14
15
11
12
9
8
10
V
U
W
R
N
P
L
M
K
T
7
5
6
3
4
H
F
G
E
C
D
1
A
B
2
J
18
0,80
0,80
PIN CONFIGURATION
Bottom View
BGA
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