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Burr Brown Products
from Texas Instruments
FEATURES
APPLICATIONS
DESCRIPTION
10-Bit
ADC
PLL
S/H
Serializer
1x ADCLK
6x ADCLK
IN1
P
ADCLK
IN1
N
OUT1
P
OUT1
N
10-Bit
ADC
S/H
Serializer
IN2
P
IN2
N
OUT2
P
OUT2
N
10-Bit
ADC
S/H
Serializer
IN3
P
IN3
N
OUT3
P
OUT3
N
LCLK
P
LCLK
N
ADCLK
P
ADCLK
N
12x ADCLK
10-Bit
ADC
S/H
Serializer
IN4
P
IN4
N
OUT4
P
OUT4
N
10-Bit
ADC
S/H
Serializer
IN5
P
IN5
N
OUT5
P
OUT5
N
10-Bit
ADC
S/H
Serializer
IN6
P
IN6
N
OUT6
P
OUT6
N
10-Bit
ADC
S/H
Serializer
IN7
P
IN7
N
OUT7
P
OUT7
N
10-Bit
ADC
S/H
Serializer
Reference
IN8
P
IN8
N
R
E
F
T
INT/EXT
V
C
M
R
E
F
B
OUT8
P
OUT8
N
Registers
S
C
L
K
S
D
A
T
A
C
S
Control
R
E
S
E
T
P
D
ADS5277
SBAS333C FEBRUARY 2005 REVISED SEPTEMBER 2005
8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter
with Serial LVDS Interface
An integrated phase lock loop (PLL) multiplies the
incoming ADC sampling clock by a factor of 12. This
Maximum Sample Rate: 65MSPS
high-frequency clock is used in the data serialization
10-Bit Resolution
and transmission process. The word output of each
internal ADC is serialized and transmitted either MSB
No Missing Codes
or LSB first. The word consists of 12 bits, of which
Total Power Dissipation:
the 2 LSBs are zeroes and the remaining 10 bits
Internal Reference: 911mW
correspond to the output from the ADC. This
External Reference: 845mW
formatting is done in order to keep the interface
CMOS Technology
compatible with the 12-bit parts of the family. In
addition to the eight data outputs, a bit clock and a
Simultaneous Sample-and-Hold
word clock are also transmitted. The bit clock is at 6x
61.7dBFS SNR at 5MHz IF
the speed of the sampling clock, whereas the word
3.3V Digital/Analog Supply
clock is at the same speed of the sampling clock.
Serialized LVDS Outputs
The ADS5277 provides internal references, or can
Integrated Frame and Bit Patterns
optionally be driven with external references. Best
performance
is
achieved
through
the
internal
Option to Double LVDS Clock Output Currents
reference mode.
Four Current Modes for LVDS
The ADS5277 is available in a PowerPAD TQFP-80
Pin- and Format-Compatible Family
package and is specified over a 40
C to +85
C
TQFP-80 PowerPADTM Package
operating range.
Portable Ultrasound Systems
Tape Drives
Test Equipment
The
ADS5277
is
a
high-performance,
CMOS,
65MSPS,
8-channel
analog-to-digital
converter
(ADC). Internal references are provided, simplifying
system design requirements. Low power consumption
allows for the highest of system integration densities.
Serial
LVDS
(low-voltage
differential
signaling)
outputs reduce the number of interface lines and
package size.
RELATED PRODUCTS
RESOLUTION
SAMPLE RATE
MODEL
(BITS)
(MSPS)
CHANNELS
ADS5270
12
40
8
ADS5271
12
50
8
ADS5272
12
65
8
ADS5273
12
70
8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
ADS5277
SBAS333C FEBRUARY 2005 REVISED SEPTEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
(2)
DESIGNATOR
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS5277IPFP
Tray, 96
ADS5277
HTQFP-80
PFP
40
C to +85
C
ADS5277IPFP
ADS5277IPFPT
Tape and Reel, 250
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com
.
(2)
Thermal pad size: 4.69mm
4.69mm (min), 6.20mm
6.20mm (max).
Analog Supply Voltage Range, AVDD
0.3V to +3.8V
Output Driver Supply Voltage Range, LVDD
0.3V to +3.8V
Voltage Between AVSS and LVSS
0.3V to +0.3V
Voltage Between AVDD and LVDD
0.3V to +0.3V
Voltage Applied to External REF Pins
0.3V to +2.4V
All LVDS Data and Clock Outputs
0.3V to +2.4V
Analog Input Pins
(2)
0.3V to min. [3.3V, (AVDD + 0.3V)]
Operating Free-Air Temperature Range, T
A
40
C to +85
C
Lead Temperature, 1.6mm (1/16" from case for 10s)
+260
C
Junction Temperature
+105
C
Storage Temperature Range
65
C to +150
C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2)
The DC voltage applied on the input pins should not go below 0.3V. Also, the DC voltage should be limited to the lower of either 3.3V
or (AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25
should be added in series with
each of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined
either as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V
and +3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not
exceed 1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
2
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RECOMMENDED OPERATING CONDITIONS
ADS5277
SBAS333C FEBRUARY 2005 REVISED SEPTEMBER 2005
ADS5277
PARAMETER
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
3.0
3.3
3.6
V
Output Driver Supply Voltage, LVDD
3.0
3.3
3.6
V
REF
T
-- External Reference Mode
1.825
1.95
2.0
V
REF
B
-- External Reference Mode
0.9
0.95
1.075
V
REFCM = (REF
T
+ REF
B
)/2 External Reference Mode
(1)
V
CM
50mV
V
Reference = (REF
T
REF
B
) External Reference Mode
0.75
1.0
1.1
V
Analog Input Common-Mode Range
(1)
V
CM
50mV
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
20
65
MSPS
ADCLK Duty Cycle
45
55
%
Low-Level Voltage Clock Input
0.6
V
High-Level Voltage Clock Input
2.2
V
ADCLK
P
and ADCLK
N
Outputs (LVDS)
20
65
MHz
LCLK
P
and LCLK
N
Outputs (LVDS)
(2)
120
390
MHz
Operating Free-Air Temperature, T
A
40
+85
C
Thermal Characteristics:
JA
19.4
C/W
JC
4.2
C/W
(1)
These voltages need to be set to 1.45V
50mV if they are derived independent of V
CM
.
(2)
6
ADCLK.
3
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ELECTRICAL CHARACTERISTICS
ADS5277
SBAS333C FEBRUARY 2005 REVISED SEPTEMBER 2005
T
MIN
= 40
C and T
MAX
= +85
C. Typical values are at T
A
= +25
C, sampling rate = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, 1dBFS, I
SET
= 56.2k
, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5277
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
Tested
DNL Differential Nonlinearity
f
IN
= 5MHz
0.5
0.08
+0.5
LSB
INL Integral Nonlinearity
f
IN
= 5MHz
1.0
0.09
+1.0
LSB
Offset Error
(1)
0.75
+0.75
%FS
Offset Temperature Coefficient
6
ppm/
C
Fixed Attenuation in Channel
(2)
1.5
%FS
Fixed Attenuation Matching Across Channels
0.01
0.2
dB
Gain Error/ Reference Error
(3)
VREF
T
VREF
B
2.5
1.0
+2.5
%FS
Gain Error Temperature Coefficient
20
ppm/
C
POWER REQUIREMENTS
(4)
Internal Reference
Power Dissipation
Analog Only (AVDD)
718
782
mW
Output Driver (LVDD)
193
218
mW
Total Power Dissipation
911
1000
mW
External Reference
Power Dissipation
Analog Only (AVDD)
652
mW
Output Driver (LVDD)
193
mW
Total Power Dissipation
845
mW
Total Power-Down
Clock Running
92
149
mW
REFERENCE VOLTAGES
VREF
T
Reference Top (internal)
1.9
1.95
2.0
V
VREF
B
Reference Bottom (internal)
0.9
0.95
1.0
V
V
CM
Common-Mode Voltage
1.4
1.45
1.5
V
V
CM
Output Current
(5)
50mV Change in Voltage
2.0
mA
VREF
T
Reference Top (external)
1.825
1.95
2.0
V
VREF
B
Reference Bottom (external)
0.9
0.95
1.075
V
External Reference Common-Mode
V
CM
50mV
V
External Reference Input Current
(6)
1.0
mA
(1)
Offset error is the deviation of the average code from mid-code with 1dBFS sinusoid from mid-code (512). Offset error is expressed in
terms of % of full-scale.
(2)
Fixed attenuation in the channel arises due to a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at the
analog input pins are changed from V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale code
(1024LSB) by the extent of this fixed attenuation. NOTE: V
REF
is defined as (REF
T
REF
B
).
(3)
The reference voltages are trimmed at production so that (VREF
T
VREF
B
) is within
25mV of the ideal value of 1V. This specification
does not include fixed attenuation.
(4)
Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
(5)
V
CM
provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The V
CM
output current
specified is the additional drive of the V
CM
buffer if loaded externally.
(6)
Average current drawn from the reference pins in the external reference mode.
4
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ADS5277
SBAS333C FEBRUARY 2005 REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
T
MIN
= 40
C and T
MAX
= +85
C. Typical values are at T
A
= +25
C, sampling rate = 65MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, 1dBFS, I
SET
= 56.2k
, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted. All values are applicable after the device has been reset.
ADS5277
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
4.0
pF
Analog Input Common-Mode Range
V
CM
50
mV
Differential Full-Scale Input Voltage Range
Internal Reference
2.03
V
PP
External Reference
2.03
(VREF
T
VREF
B
)
V
PP
Voltage Overload Recovery Time
(7)
3.0
CLK Cycles
3dBFS, 25
Series
Input Bandwidth
300
MHz
Resistances
DIGITAL INPUTS
V
IH
High Level Input Voltage
2.2
V
V
IL
Low Level Input Voltage
0.6
V
C
IN
Input Capacitance
3
pF
DIGITAL DATA OUTPUTS
Data Format
Straight Offset Binary
Data Bit Rate
240
780
Mbps
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
20
MHz
(7)
A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
Internal Reference; FSR = 2.03V
PP
1
Default with internal pull-up.
Internal reference is powered down. The common-mode voltage
External Reference; FSR = 2.03
(VREF
T
VREF
B
)
0
of the external reference should be within 50mV of V
CM
. V
CM
is
derived from the internal bandgap voltage.
5
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