ADS5413
SLWS153 - DECEMBER 2003
SINGLE 12-BIT, 65-MSPS IF SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
D
12-Bit Resolution
D
65-MSPS Maximum Sample Rate
D
2-Vpp Differential Input Range
D
3.3-V Single Supply Operation
D
1.8-V to 3.3-V Output Supply
D
400-mW Total Power Dissipation
D
Two's Complement Output Format
D
On-Chip S/H and Duty Cycle Adjust Circuit
D
Internal or External Reference
D
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
D
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS
and 190-MHz Input
D
Power-Down Mode
D
Single-Ended or Differential Clock
D
1-GHz -3-dB Input Bandwidth
APPLICATIONS
D
High IF Sampling Receivers
D
Medical Imaging
D
Portable Instrumentation
DESCRIPTION
The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a
single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and
low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit
allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous
sampling. The device can also be clocked with single ended or differential clock, without change in performance. The
internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the
application.
The device is specified over full temperature range (-40
C to +85C).
FUNCTIONAL BLOCK DIAGRAM
Digital Error Correction
7 Stages
Internal
Reference
Generator
1.8 V
1.25 V
DCA
CML
VBG
CLK
AGND
D[0:11]
AVDD
A/D
D/A
A/D
VREFB
CLKC
2
2
OVDD
OGND
S/H
VREFT
2.25 V
D/A
A/D
2
VINP
VINN
Gain
Stage
Gain
Stage
D/A
A/D
2
Gain
Stage
Flash
PWD
REF SEL
DCA
CommsADC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2003, Texas Instruments Incorporated
ADS5413
SLWS153 - DECEMBER 2003
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
PACKAGE LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5413
HTQFP-48
(2)
PowerPAD
PHP
-40
C to 85C
AZ5413
ADS5413IPHP
Tray, 250
(1)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2)
Thermal pad size: 3,5 mm
3,5 mm
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNITS
Supply voltage range
AVDD measured with respect to AGND
-0.3 V to 3.9 V
Supply voltage range
OVDD measure with respect to OGND
-0.3 V to 3.9 V
Digital input, measured with respect to AGND
-0.3 V to AVDD + 0.3 V
Reference inputs Vrefb or Vreft, measured with respect to AGND
-0.3 V to AVDD + 0.3 V
Analog inputs Vinp or Vinn, measured with respect to AGND
-0.3 V to AVDD + 0.3 V
Maximum storage temperature
150
C
Soldering reflow temperature
235
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
NOM
MAX
UNIT
ENVIRONMENTAL
Operating free-air temperature, T
A
-40
85
C
SUPPLIES
Analog supply voltage, V
(AVDD)
3
3.3
3.6
V
Output driver supply voltage, V
(OVDD)
1.6
3.6
V
ANALOG INPUTS
Input common-mode voltage
CML
(2)
V
Differential input voltage range
2
V
PP
CLOCK INPUTS, CLK AND CLKC
Sample rate, f
S
= 1/t
c
5
65
MHz
Differential input swing
(see Figure 17)
1
6
V
PP
Differential input common-mode voltage (see Figure 18)
1.65
V
Clock pulse width high, t
w(H)
(see Figure 16, with DCA off)
6.92
ns
Clock pulse width low, t
w(L)
(see Figure 16, with DCA off)
6.92
ns
(1)
Recommended by design and characterization but not tested at final production unless specified under the
electrical characteristics
section.
(2)
See V
(CML)
in the internal reference generator section.
ADS5413
SLWS153 - DECEMBER 2003
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3
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, A
IN
= -1 dBFS, 1.2-V
PP
square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
Power Supply
Total analog supply current with internal
reference and DCA on
113
I
(AVDD)
Analog supply current with external reference
and DCA on
A
IN
= 0 dBFS, f
IN
= 2 MHz
96
mA
Analog supply current with internal and DCA off
reference
107
I
(OVDD)
Digital output driver supply current
A
IN
= 0 dBFS, f
IN
= 2 MHz
8
mA
P
D
Total power dissipation
A
IN
= 0 dBFS, f
IN
= 2 MHz
400
480
mW
P
D
Power down dissipation
PWDN = high
23
50
mW
DC Accuracy
No missing codes
Assured
DNL
Differential nonlinearity
Sinewave input, f
IN
= 2 MHz
-0.9
0.5
1
LSB
INL
Integral nonlinearity
Sinewave input, f
IN
= 2 MHz
-2
1
2
LSB
E
O
Offset error
Sinewave input, f
IN
= 2 MHz
3
mV
E
G
Gain error
Sinewave input, f
IN
= 2 MHz
0.3
%FS
Internal Reference Generator
V
REFB
Reference bottom
1.1
1.25
1.4
V
V
REFT
Reference top
2.1
2.25
2.4
V
V
REFT
- V
REFB
1.06
V
V
REFT
- V
REFB
variation (6
)
0.06
V
V
(CML)
Common-mode output voltage
1.8
V
Digital Inputs (PWD, DCA, REF SEL)
I
IH
High-level input current
V
I
= 2.4 V
-60
60
A
I
IL
Low-level input current
V
I
= 0.3 V
-60
60
A
V
IH
High-level input voltage
2
V
V
IL
Low-level input voltage
0.8
V
Digital Outputs
V
OH
High-level output voltage
I
OH
= 50
A
2.4
V
V
OL
Low-level output voltage
I
OL
= -50
A
0.8
V
AC PERFORMANCE
f
IN
= 14 MHz
63
68.5
f
IN
= 39 MHz
68.5
SNR
Signal-to-noise ratio
f
IN
= 70 MHz
68.2
dBFS
SNR
Signal to noise ratio
f
IN
= 150 MHz
64.8
dBFS
f
IN
= 220 MHz
63.8
f
IN
= 14 MHz
62.5
67.6
f
IN
= 39 MHz
67.8
SINAD
Signal-to-noise and distortion
f
IN
= 70 MHz
67.9
dBFS
SINAD
Signal to noise and distortion
f
IN
= 150 MHz
63.2
dBFS
f
IN
= 220 MHz
63
f
IN
= 14 MHz
72
77.5
f
IN
= 39 MHz
79
SFDR
Spurious free dynamic range
f
IN
= 70 MHz
81
dBc
p
y
g
f
IN
= 150 MHz
69
f
IN
= 220 MHz
72
ADS5413
SLWS153 - DECEMBER 2003
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4
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, A
IN
= -1 dBFS, 1.2-V
PP
square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (Continued)
f
IN
= 14 MHz
90
f
IN
= 39 MHz
90
HD2
Second order harmonic
f
IN
= 70 MHz
90
dBc
HD2
Second order harmonic
f
IN
= 150 MHz
83
dBc
f
IN
= 220 MHz
72
f
IN
= 14 MHz
77.5
f
IN
= 39 MHz
79
HD3
Third order harmonic
f
IN
= 70 MHz
81
dBc
HD3
Third order harmonic
f
IN
= 150 MHz
69
dBc
f
IN
= 220 MHz
77
Two tone IMD rejection, A
1,2
= -7 dBFS
f
1
= 220 MHz,
f
2
= 225 MHz
69
dBc
Analog input bandwidth
-3 dB BW respect to -3 dBFS input at low
frequency
1
GHz
TIMING CHARACTERISTICS
25
C, C
L
= 10 pF
MIN
TYP
MAX
UNIT
t
Aperture delay
2
ns
t
d(A)
Aperture jitter
0.4
ps
t
d(Pipe)
Latency
6
Cycles
t
d1
Propagation delay from clock input to beginning of data stable
(1)
DCS off OVDD 1 8 V
8
ns
t
d2
Propagation delay from clock input to end of data stable
(1)
DCS off, OVDD = 1.8 V
20.3
ns
t
d1
Propagation delay from clock input to beginning of data stable
(1)
DCS off OVDD 3 3 V
7
ns
t
d2
Propagation delay from clock input to end of data stable
(1)
DCS off, OVDD = 3.3 V
20.3
ns
t
d1
Propagation delay from clock input to beginning of data stable
(1)
DCS on OVDD 1 8 V
10
ns
t
d2
Propagation delay from clock input to end of data stable
(1)
DCS on, OVDD = 1.8 V
22.3
ns
t
d1
Propagation delay from clock input to beginning of data stable
(1)
DCS on OVDD 3 3 V
9
ns
t
d2
Propagation delay from clock input to end of data stable
(1)
DCS on, OVDD = 3.3 V
22.3
ns
(1)
Data stable if V
O
< 10% OVDD or V
O
> 90% OVDD
TIMING DIAGRAM
VINP
CLK
D[0:11]
Data N-7
t
w(H)
t
w(L)
t
d(A)
Sample N
t
c
t
d2(O)
t
d(Pipe)
Data N-6
Data N-5
Data N-4
Data N-3
Data N-2
Data N-1
Data N
Data N+1
Data N+2
t
d1(O)
Figure 1. ADS5413 Timing Diagram
ADS5413
SLWS153 - DECEMBER 2003
www.ti.com
5
PIN ASSIGNMENTS
14 15
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 (MSB)
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
AVDD
AGND
VINP
VINN
AGND
CML
AVDD
VREFB
VREFT
AVDD
AGND
NC
17 18 19 20
47 46 45 44 43
48
42
40 39 38
41
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
REF SEL
A
VDD
AGND
A
VDD
A
VDD
AGND
AGND
AGND
A
VDD
OGND
OVDD
NC
VBG
NC
DECOUPLING
PWD
NC
A
VDD
CLK
CLKC
AGND
OGND
OVDD
DCA
THERMAL PAD
(Connect to GND Plane)
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD
1, 7, 10, 18,
40, 44, 45, 47
I
Analog power supply
AGND
2, 5, 11, 21,
41, 42, 43, 46
I
Analog ground
CLK
19
I
Clock input
CLKC
20
I
Complementary clock input
CML
6
O
Common-mode output voltage
D11-D0
25-36
O
Digital outputs, D11 is most significant data bit, D0 is least significant data bit.
DCA
24
I
Duty cycle adjust control. High = enable, low = disable, NC = enable
DECOUPLING
15
O
Decoupling pin. Add 0.1
F to GND
NC
12, 14, 17, 37
Internally not connected
OGND
22, 39
I
Digital driver ground
OVDD
23, 38
I
Digital driver power supply
PWD
16
I
Power down. High = powered down, low = powered up, NC = powered up
REF SEL
48
I
Reference select. High = external reference, low = internal reference, NC = internal reference
VBG
13
O
Bandgap voltage output
VINN
4
I
Complementary analog input
VINP
3
I
Analog input
VREFB
8
I/O
Reference bottom
VREFT
9
I/O
Reference top
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