SLWS160 - FEBRUARY 2005
14 Bit, 80 MSPS
Analog-to-Digital Converter
ADS5423
FEATURES
D
14 Bit Resolution
D
80 MSPS Maximum Sample Rate
D
SNR = 74 dBc at 80 MSPS and 50 MHz IF
D
SFDR = 94 dBc at 80 MSPS and 50 MHz IF
D
2.2 V
pp
Differential Input Range
D
5 V Supply Operation
D
3.3 V CMOS Compatible Outputs
D
1.85 W Total Power Dissipation
D
2s Complement Output Format
D
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
D
52 Pin HTQFP Package With Exposed
Heatsink
D
Pin Compatible to the AD6644/45
D
Industrial Temperature Range = -405C to 855C
APPLICATIONS
D
Single and Multichannel Digital Receivers
D
Base Station Infrastructure
D
Instrumentation
D
Video and Imaging
RELATED DEVICES
D
Clocking: CDC7005
D
Amplifiers: OPA695, THS4509
DESCRIPTION
The ADS5423 is a 14 bit 80 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing 3.3 V
CMOS compatible digital outputs. The ADS5423 input buffer isolates the internal switching of the on-chip Track and Hold
(T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5423 has outstanding low noise and linearity, over input frequency. With only a 2.2 V
PP
input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5423 is available in a 52 pin HTQFP with heatsink package and is pin compatible to the AD6645. The ADS5423
is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full industrial
temperature range (-40C to 85C).
FUNCTIONAL BLOCK DIAGRAM
Reference
Timing
CLK+
OVR
D[13:0]
CLK-
6
DMID
DRY
VREF
A
IN
A
IN
TH1
5
5
DAC2
ADC2
ADC3
DAC1
ADC1
A3
A1
TH2
TH3
C1
C2
AV
DD
DRV
DD
GND
Digital Error Correction
A2
+
-
+
-
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
www.ti.com
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Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
ADS5423
SLWS160 - FEBRUARY 2005
www.ti.com
2
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5423
HTQFP-52
(1)
PJY
40C to 85C
ADS5423I
ADS5423IPJY
Tray, 160
ADS5423
HTQFP 52
( )
PowerPAD
PJY
-40C to +85C
ADS5423I
ADS5423IPJYR
Tape and Reel, 1000
(1)
Thermal pad size: Octagonal 2,5 mm side
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
ADS5423
UNIT
Supply voltage
AV
DD
to GND
6
V
Supply voltage
DRV
DD
to GND
5
V
Analog input to GND
-0.3 to
AV
DD
+ 0.3
V
Clock input to GND
-0.3 to
AV
DD
+ 0.3
V
CLK to CLK
2.5
V
Digital data output to GND
-0.3 to
DRV
DD
+ 0.3
V
Operating temperature range
-40 to 85
C
Maximum junction temperature
150
C
Storage temperature range
-65 to 150
C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
THERMAL CHARACTERISTICS
(1)
PARAMETER
TEST
CONDITIONS
TYP
UNIT
JA
Soldered slug, no
airflow
22.5
C/W
JA
Soldered slug,
200-LPFM airflow
15.8
C/W
JA
Unsoldered slug,
no airflow
33.3
C/W
JA
Unsoldered slug,
200-LPFM airflow
25.9
C/W
JC
Bottom of
package
(heatslug)
2
C/W
(1)
Using 25 thermal vias (5 x 5 array). See the Application Section.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Supplies
Analog supply voltage, AV
DD
4.75
5
5.25
V
Output driver supply voltage,
DRV
DD
3
3.3
3.6
V
Analog Input
Differential input range
2.2
V
PP
Input common-mode voltage,
V
CM
2.4
V
Digital Output
Maximum output load
10
pF
Clock Input
ADCLK input sample rate (sine
wave) 1/t
C
30
80
MSPS
Clock amplitude, sine wave,
differential
(1)
3
V
PP
Clock duty cycle
(2)
50%
Open free-air temperature range
-40
85
C
(1)
See Figure 17 and Figure 18 for more information.
(2)
See Figure 16 for more information.
ADS5423
SLWS160 - FEBRUARY 2005
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3
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
MIN
= -40C to T
MAX
= 85C), sampling rate = 80 MSPS, 50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V,
-1 dBFS differential input, and 3 V
PP
differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
Analog Inputs
Differential input range
2.2
V
PP
Differential input resistance
See Figure 30
1
k
Differential input capacitance
See Figure 30
1.5
pF
Analog input bandwidth
570
MHz
Internal Reference Voltages
Reference voltage, V
REF
2.4
V
Dynamic Accuracy
No missing codes
Tested
Differential linearity error, DNL
f
IN
= 5 MHz
-0.95
0.5
1.5
LSB
Integral linearity error, INL
f
IN
= 5 MHz
1.5
LSB
Offset error
-5
0
5
mV
Offset temperature coefficient
1.7
ppm/C
Gain error
-5
0.9
5
%FS
PSRR
1
mV/V
Gain temperature coefficient
77
ppm/C
Power Supply
Analog supply current, I
AVDD
V
IN
= full scale, f
IN
= 70 MHz
355
410
mA
Output buffer supply current, I
DRVDD
V
IN
= full scale, f
IN
= 70 MHz
35
42
mA
Power dissipation
Total power with 10-pF load on each digital output
to ground, f
IN
= 70 MHz
1.85
2.2
W
Power-up time
20
100
ms
Dynamic AC Characteristics
f
IN
= 10 MHz
74.6
f
IN
= 30 MHz
73
74.3
f
IN
= 50 MHz
74.2
Signal-to-noise ratio, SNR
f
IN
= 70 MHz
73
74.1
dBc
Signal to noise ratio, SNR
f
IN
= 100 MHz
73.5
dBc
f
IN
= 170 MHz
72
f
IN
= 230 MHz
71.5
f
IN
= 10 MHz
94
f
IN
= 30 MHz
85
93
f
IN
= 50 MHz
94
Spurious-free dynamic range, SFDR
f
IN
= 70 MHz
90
dBc
p
y
g ,
f
IN
= 100 MHz
86
f
IN
= 170 MHz
73
f
IN
= 230 MHz
64
ADS5423
SLWS160 - FEBRUARY 2005
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4
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
MIN
= -40C to T
MAX
= 85C), sampling rate = 80 MSPS, 50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V,
-1 dBFS differential input, and 3 V
PP
differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
IN
= 10 MHz
74.6
f
IN
= 30 MHz
72.8
74.2
f
IN
= 50 MHz
74.1
Signal-to-noise + distortion, SINAD
f
IN
= 70 MHz
73.9
dBc
Signal to noise + distortion, SINAD
f
IN
= 100 MHz
72.7
dBc
f
IN
= 170 MHz
69.1
f
IN
= 230 MHz
62.8
f
IN
= 10 MHz
105
f
IN
= 30 MHz
100
f
IN
= 50 MHz
99
Second harmonic, HD2
f
IN
= 70 MHz
92
dBc
Second harmonic, HD2
f
IN
= 100 MHz
90
dBc
f
IN
= 170 MHz
94
f
IN
= 230 MHz
88
f
IN
= 10 MHz
94
f
IN
= 30 MHz
93
f
IN
= 50 MHz
94
Third harmonic, HD3
f
IN
= 70 MHz
90
dBc
Third harmonic, HD3
f
IN
= 100 MHz
86
dBc
f
IN
= 170 MHz
73
f
IN
= 230 MHz
64
f
IN
= 10 MHz
94
f
IN
= 30 MHz
95
Worst harmonic / spur (other than HD2 and
f
IN
= 50 MHz
95
Worst-harmonic / spur (other than HD2 and
HD3)
f
IN
= 70 MHz
90
dBc
HD3)
f
IN
= 100 MHz
88
dBc
f
IN
= 170 MHz
88
f
IN
= 230 MHz
88
RMS idle channel noise
Input pins tied together
0.9
LSB
DIGITAL CHARACTERISTICS
Over full temperature range (T
MIN
= -40C to T
MAX
= 85C), AV
DD
= 5 V, DRV
DD
= 3.3 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Outputs
Low-level output voltage
C
LOAD
= 10 pF
(1)
0.1
0.6
V
High-level output voltage
C
LOAD
= 10 pF
(1)
2.6
3.2
V
Output capacitance
3
pF
DMID
DRV
DD
/2
V
(1)
Equivalent capacitance to ground of (load + parasitics of transmission lines).
ADS5423
SLWS160 - FEBRUARY 2005
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5
TIMING CHARACTERISTICS
(3)
Over full temperature range, AV
DD
= 5 V, DRV
DD
= 3.3 V, sampling rate = 80 MSPS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Aperture Time
t
A
Aperture delay
500
ps
t
J
Clock slope independent aperture uncertainity (jitter)
150
fs
k
J
Clock slope dependent jitter factor
50
V
Clock Input
t
CLK
Clock period
12.5
ns
t
CLKH
(1)
Clock pulsewidth high
6.25
ns
t
CLKL
(1)
Clock pulsewidth low
6.25
ns
Clock to DataReady (DRY)
t
DR
Clock rising 50% to DRY falling 50%
2.8
3.9
4.7
ns
t
C_DR
Clock rising 50% to DRY rising 50%
t
DR
+
t
CLKH
ns
t
C_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
9
10.1
11
ns
Clock to DATA, OVR
(4)
t
r
Data V
OL
to data V
OH
(rise time)
2
ns
t
f
Data V
OH
to data V
OL
(fall time)
2
ns
L
Latency
3
Cycles
t
su(C)
Valid DATA
(2)
to clock 50% with 50% duty cycle clock (setup time)
4.8
6.3
ns
t
H(C)
Clock 50% to invalid DATA
(2)
(hold time)
2.6
3.6
ns
DataReady (DRY) to DATA, OVR
(4)
t
su(DR)_50%
Valid DATA
(2)
to DRY 50% with 50% duty cycle clock (setup time)
3.3
4
ns
t
h(DR)_50%
DRY 50% to invalid DATA
(2)
with 50% duty cycle clock (hold time)
5.4
5.9
ns
(1)
See Figure 1 for more information.
(2)
See V
OH
and V
OL
levels.
(3)
All values obtained from design and characterization.
(4)
Data is updated with clock rising edge or DRY falling edge.
N
N+1
N+2
N+3
N+4
N
N-1
N-2
N-3
t
A
t
su(C)
t
h(C)
t
h(DR)
N + 1
N
N + 2
N + 3
N + 4
t
C_DR
t
r
t
CLK
t
CLKL
CLK, CLK
D[13:0], OVR
DRY
AIN
t
CLKH
t
DR
t
su(DR)
t
f
Figure 1. Timing Diagram
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