Document Outline

• Title Page - SBAS253B
• IMPORTANT NOTICE
• Contents
• List of Illustrations
• List of Tables
• FEATURES
• APPLICATIONS
• DESCRIPTION
  • 1.1 ORDERING INFORMATION(1)
  • 1.2 ABSOLUTE MAXIMUM RATINGS
  • 1.3 RECOMMENDED OPERATING CONDITIONS
  • 1.4 PACKAGE DISSIPATION RATINGS
  • 1.5 ELECTRICAL CHARACTERISTICS
  • 1.6 PINOUT DRAWING
    • TQFP Package
  • 1.7 PIN FUNCTIONS
    • TQFP Package
  • 1.8 BASIC CIRCUIT CONFIGURATION
  • 1.9 TYPICAL APPLICATION CIRCUIT
  • 1.10 TYPICAL CHARACTERISTICS
  • 1.11 FUNCTIONAL BLOCK DIAGRAM
• 2 Analog Section
  • 2.1 Fully Differential Analog Inputs
    • 2.1.1 Analog-to-Digital Converter Inputs
    • 2.1.2 Window Comparator Inputs
    • 2.1.3 Sign Comparator Inputs
  • 2.2 Analog-To-Digital Converter
    • 2.2.1 HOLD1\, HOLD2\
    • 2.2.2 Clock
    • 2.2.3 Reset
    • 2.2.4 Gain Adjustment
    • 2.2.5 Offset Adjustment
    • 2.2.6 Transition Noise
  • 2.3 Sign Comparators
  • 2.4 Window Comparators
  • 2.5 8-Bit Digital-to-Analog Converter
  • 2.6 Internal Reference
  • 2.7 Grounding
  • 2.8 Supply
• 3 Digital Section
  • 3.1 Introduction
  • 3.2 VECANA Interface
    • 3.2.1 Input Channel Selection
      • Input Select = 0H
      • Input Select = 1H
      • Input Select = 2H
      • Input Select = 3H
      • Input Select = 4H, 5H and 6H
      • Input Select = 7H
    • 3.2.2 VECANA Timing Characteristics(1)
    • 3.2.3 WINCLK Selection
  • 3.3 Serial Peripheral Interface (SPI)
    • 3.3.1 SPI Timing Characteristics(1)
  • 3.4 Parallel Interface
    • 3.4.1 Parallel Read and Write Control
    • 3.4.2 Mode 10 Bus Access
      • 3.4.2.1 Read Timing Characteristics (1)
      • 3.4.2.2 Write Timing Characteristics (1)
    • 3.4.3 Mode 11 Bus Access ( Standard Mode)
      • 3.4.3.1 Read Timing Characteristics (1)
      • 3.4.3.2 Write Timing Characteristics (1)
    • 3.4.4 Mode 11 Bus Access ( TMS320c54xx DSP Family-Compatible Mode)
      • 3.4.4.1 Read Timing Characteristics (1)
      • 3.4.4.2 Write Timing Characteristics (1)
  • 3.5 Register Map
  • 3.6 Register Descriptions
    • 3.6.1 FIFO Data Register ( 00H)
    • 3.6.2 Offset Registers ( 01H � 0CH)
    • 3.6.3 Gain Registers ( 0DH to 18H)
    • 3.6.4 WINDAC Register ( 19H)
    • 3.6.5 Control Register ( 1AH)
    • 3.6.6 Counter Control/Status Register ( 1BH)
    • 3.6.7 Edge Count Register ( 1CH, 1DH, 20H and 21H)
    • 3.6.8 Edge Period Register ( 1EH and 22H)
    • 3.6.9 Edge Time Period Register ( 1FH and 23H)
    • 3.6.10 FIFO Test Register ( 24H)
    • 3.6.11 Comparator Test Register ( 25H)
    • 3.6.12 Interrupt Register ( 26H)
    • 3.6.13 Parallel Register ( 27H)
    • 3.6.14 Reset Register ( 28H)
  • 3.7 FIFO
    • 3.7.1 DAV Timing Characteristics (1)
  • 3.8 Digital Counter Modules
    • 3.8.1 Operation
    • 3.8.2 Digital Noise Filter
      • 3.8.2.1 Filtered Timing Characteristics (1)
      • 3.8.2.2 Unfiltered Timing Characteristics (1)
    • 3.8.3 Binary Counters and Registers
  • 3.9 Interrupt
  • 3.10 Reset
    • 3.10.1 Reset Timing Characteristics( 1)