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Burr Brown Products
from Texas Instruments
FEATURES
APPLICATIONS
DESCRIPTION
ADS7886
SLAS492 SEPTEMBER 2005
12-Bit, 1-MSPS, MICRO-POWER, MINIATURE
SAR ANALOG-TO-DIGITAL CONVERTERS
Base Band Converters in Radio
1-MHz Sample Rate Serial Device
Communication
12-Bit Resolution
Motor Current/Bus Voltage Sensors in Digital
Zero Latency
Drives
20-MHz Serial Interface
Optical Networking (DWDM, MEMS Based
Supply Range: 2.35 V to 5.25 V
Switching)
Typical Power Dissipation at 1 MSPS:
Optical Sensors
Battery Powered Systems
3.9 mW at 3-V V
DD
Medical Instrumentations
7.5 mW at 5-V V
DD
High-Speed Data Acquisition Systems
INL
1.25 LSB Maximum,
0.65 LSB (Typical)
High-Speed Closed-Loop Systems
DNL
1 LSB Maximum, +0.4 / -0.65 LSB
(Typical)
Typical AC Performance:
72.25 dB SINAD, -84 dB THD
Unipolar Input Range: 0 V to V
DD
Power Down Current: 1 A
Wide Input Bandwidth: 15 MHz at 3 dB
6-Pin SOT23 and SC70 Packages
The ADS7886 is a 12-bit, 1-MSPS analog-to-digital converter (ADC). The device includes a capacitor based SAR
A/D converter with inherent sample and hold. The serial interface in each device is controlled by the CS and
SCLK signals for glueless connections with microprocessors and DSPs. The input signal is sampled with the
falling edge of CS, and SCLK is used for conversion and serial data output.
The device operates from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the device
makes it suitable for battery-powered applications. The device also includes a powerdown feature for power
saving at lower conversion speeds.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go as
high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other
circuit with different supply levels. Also this relaxes restriction on power up sequencing.
The ADS7886 is available in 6-pin SOT23 and SC70 packages and is specified for operation from -40C to
125C.
Micro-Power Miniature SAR Converter Family
BIT
< 300 KSPS
300 KSPS 1.25 MSPS
12-Bit
ADS7866 (1.2 V
DD
to 3.6 V
DD
)
ADS7886 (2.35 V
DD
to 5.25 V
DD
)
10-Bit
ADS7867 (1.2 V
DD
to 3.6 V
DD
)
ADS7887 (2.35 V
DD
to 5.25 V
DD
)
8-Bit
ADS7868 (1.2 V
DD
to 3.6 V
DD
)
ADS7888 (2.35 V
DD
to 5.25 V
DD
)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
SCLK
+IN
VDD
CDAC
SAR
COMPARATOR
OUTPUT
LATCHES
and
DRIVERS
3!STATE
CONVERSION
and
CONTROL
LOGIC
SDO
CS
ADS7886
SLAS492 SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUM
NO MISSING
PACK-
DIFFER-
PACK-
TRANSPORT
INTEGRAL
CODES AT
AGE
TEMPERATURE
PACKAGE
ORDERING
DEVICE
ENTIAL
AGE
MEDIA
LINEARITY
RESOLUTION
DESIG-
RANGE
MARKING
INFORMATION
LINEARITY
TYPE
QUANTITY
(LSB)
(BIT)
NATOR
(LSB)
Tape and
ADS7886SBDBVT
reel 250
6-Pin
DBV
BBAQ
SOT23
Tape and
ADS7886SBDBVR
reel 3000
ADS7886SB
1.25
1
12
40
C to 125
C
Tape and
ADS7886SBDCKT
reel 250
6-Pin
DCK
BNL
SC70
Tape and
ADS7886SBDCKR
reel 3000
Tape and
ADS7886SDBVT
reel 250
6-Pin
DBV
BBAQ
SOT23
Tape and
ADS7886SDBVR
reel 3000
ADS7886S
2
2
11
40
C to 125
C
Tape and
ADS7886SDCKT
reel 250
6-Pin
DCK
BNL
SC70
Tape and
ADS7886SDCKR
reel 3000
(1)
For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2
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ABSOLUTE MAXIMUM RATINGS
(1)
ELECTRICAL CHARACTERISTICS
ADS7886
SLAS492 SEPTEMBER 2005
UNIT
+IN to AGND
0.3 V to +V
DD
+0.3 V
+V
DD
to AGND
0.3 V to 7 V
Digital input voltage to GND
0.3 V to (7 V)
Digital output to GND
0.3 V to (+V
DD
+ 0.3 V)
Operating temperature range
40
C to 125
C
Storage temperature range
65
C to 150
C
Junction temperature (T
J
Max)
150C
Power dissipation, SOT23 and SC70 packages
(T
J
MaxT
A
)/
JA
SOT23
295.2
C/W
JA
Thermal impedance
SC70
351.3
C/W
Vapor phase (60 sec)
215
C
Lead temperature, soldering
Infrared (15 sec)
220
C
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
+V
DD
= 2.35 V to 5.25 V, T
A
= 40
C to 125
C, f
(sample)
= 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0
V
DD
V
Absolute input voltage range
+IN
0.2
V
DD
+0.2
V
C
I
Input capacitance
(2)
21
pF
I
lkg
Input leakage current
T
A
= 125
C
40
nA
SYSTEM PERFORMANCE
Resolution
12
Bits
ADS7886SB
12
No missing codes
Bits
ADS7886S
11
ADS7886SB
1.25
0.65
1.25
INL
Integral nonlinearity
LSB
(3)
ADS7886S
2
2
ADS7886SB
1
+0.4/-0.65
1
DNL
Differential nonlinearity
LSB
ADS7886S
-2
2
V
DD
= 2.35 V to 3.6 V
2.5
0.5
2.5
E
O
Offset error
(4)
LSB
V
DD
= 4.75 V to 5.25 V
-2
0.5
2
E
G
Gain error
1.75
0.5
1.75
LSB
SAMPLING DYNAMICS
Conversion time
20-MHz SCLK
760
800
ns
Acquisition time
325
ns
Maximum throughput rate
20-MHz SCLK
1
MHz
Aperture delay
5
ns
Step Response
160
ns
Overvoltage recovery
160
ns
DYNAMIC CHARACTERISTICS
V
DD
= 2.35 V to 3.6 V, f
I
= 100 kHz
69
71.25
SNR
Signal-to-noise ratio
dB
V
DD
= 4.75 V to 5.25 V, f
I
= 100 kHz
70
72.25
(1)
Ideal input span; does not include gain or offset error.
(2)
See
Figure 28
for details on the sampling circuit.
(3)
LSB means least significant bit.
(4)
Measured relative to an ideal full-scale input.
3
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ADS7886
SLAS492 SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
+V
DD
= 2.35 V to 5.25 V, T
A
= 40
C to 125
C, f
(sample)
= 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
DD
= 2.35 V to 3.6 V, f
I
= 100 kHz
69
71.25
SINAD
Signal-to-noise and distortion
dB
V
DD
= 4.75 V to 5.25 V, f
I
= 100 kHz
70
72.25
THD
Total harmonic distortion
(5)
f
I
= 100 kHz
84
dB
SFDR
Spurious free dynamic range
f
I
= 100 kHz
85.5
dB
Full power bandwidth
At 3 dB
15
MHz
DIGITAL INPUT/OUTPUT
Logic family -- CMOS
V
IH
High-level input voltage
V
DD
= 2.35 V to 5.25 V
V
DD
0.4
5.25
V
V
DD
= 5 V
0.8
V
IL
Low-level input voltage
V
V
DD
= 3 V
0.4
V
OH
High-level output voltage
I
(source)
= 200 A
V
DD
0.2
V
V
OL
Low-level output voltage
I
(sink)
= 200 A
0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage
2.35
3.3
5.25
V
V
DD
= 2.35 V to 3.6 V, 1-MHz
1.3
1.5
throughput
V
DD
= 4.75 V to 5.25 V, 1-MHz
1.5
2
Supply current (normal mode)
mA
throughput
V
DD
= 2.35 V to 3.6 V, static state
1.1
V
DD
= 4.75 V to 5.25 V, static state
1.5
SCLK off
1
Power down state supply current
A
SCLK on (20 MHz)
200
V
DD
= 3 V
3.9
4.5
Power dissipation at 1-MHz throughput
mW
V
DD
= 5 V
7.5
10
V
DD
= 3 V
3.3
Power dissipation in static state
mW
V
DD
= 5 V
7.5
Power up time
0.1
s
Invalid conversions after
1
power up or reset
(5)
Calculated on the first nine harmonics of the input frequency.
4
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TIMING REQUIREMENTS (see
Figure 1
and
Figure 2
)
ADS7886
SLAS492 SEPTEMBER 2005
All specifications typical at T
A
= 40
C to 125
C, V
DD
= 2.35 V to 5.25 V (unless otherwise specified).
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
V
DD
= 3 V
16
t
SCLK
t
conv
Conversion time
ADS7866
ns
V
DD
= 5 V
16
t
SCLK
V
DD
= 3 V
40
Minimum quiet time needed from bus 3-state to start
t
q
ns
of next conversion
V
DD
= 5 V
40
V
DD
= 3 V
15
25
t
d1
Delay time, CS low to first data (0) out
ns
V
DD
= 5 V
13
25
V
DD
= 3 V
10
t
su1
Setup time, CS low to SCLK low
ns
V
DD
= 5 V
10
V
DD
= 3 V
15
25
t
d2
Delay time, SCLK falling to SDO
ns
V
DD
= 5 V
13
25
V
DD
< 3 V
7
t
h1
Hold time, SCLK falling to data valid
(2)
ns
V
DD
> 5 V
5.5
V
DD
= 3 V
10
25
t
d3
Delay time, 16th SCLK falling edge to SDO 3-state
ns
V
DD
= 5 V
8
20
V
DD
= 3 V
25
40
t
w1
Pulse duration, CS
ns
V
DD
= 5 V
25
40
V
DD
= 3 V
17
30
t
d4
Delay time, CS high to SDO 3-state
ns
V
DD
= 5 V
15
25
V
DD
= 3 V
0.4
t
SCLK
t
wH
Pulse duration, SCLK high
ns
V
DD
= 5 V
0.4
t
SCLK
V
DD
= 3 V
0.4
t
SCLK
t
wL
Pulse duration, SCLK low
ns
V
DD
= 5 V
0.4
t
SCLK
V
DD
= 3 V
20
Frequency, SCLK
MHz
V
DD
= 5 V
20
Delay time, second falling edge of clock and CS to
V
DD
= 3 V
-2
5
t
d5
enter in powerdown (use min spec not to accidently
ns
V
DD
= 5 V
-2
5
enter in powerdown)
Figure 2
Delay time, CS and 10th falling edge of clock to
V
DD
= 3 V
2
-5
t
d6
enter in powerdown (use max spec not to accidently
ns
V
DD
= 5 V
2
-5
enter in powerdown)
Figure 2
(1)
3-V Specifications apply from 2.35 V to 3.6 V, and 5-V specifications apply from 4.75 V to 5.25 V.
(2)
With 50-pf load.
5
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