ChipFind - документация

Электронный компонент: ADS8364Y/2K

Скачать:  PDF   ZIP
ADS8364: 250kHz, 16-Bit, 6-Channel Simultaneous Sampling A/D Converters (Rev. B)
background image
250kHz, 16-Bit, 6-Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q
6 INPUT CHANNELS
q
FULLY DIFFERENTIAL INPUTS
q
6 INDEPENDENT 16-BIT ADC
q
4
s TOTAL THROUGHPUT PER CHANNEL
q
TESTED NO MISSING CODES TO 14 BITS
q
BUFFERED REFERENCE INPUTS
q
LOW POWER: 450mW
q
TQFP-64 PACKAGE
APPLICATIONS
q
MOTOR CONTROL
q
MULTI-AXIS POSITIONING SYSTEMS
q
3-PHASE POWER CONTROL
DESCRIPTION
The ADS8364 includes six, 16-bit, 250KHz ADCs (Analog-to-
Digital converters) with 6 fully differential input channels
grouped into two pairs for high-speed simultaneous signal
acquisition. Inputs to the sample-and-hold amplifiers are fully
differential and are maintained differential to the input of the
ADC. This provides excellent common-mode rejection of
80dB at 50KHz that is important in high-noise environments.
The ADS8364 offers a flexible high-speed parallel interface
with a direct address mode, a cycle, and a FIFO mode. The
output data for each channel is available as a 16-bit word.
ADS8364
SBAS219B JUNE 2002 REVISED JULY 2004
www.ti.com
Copyright 2002-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS836
4
Interface
Conversion
and
Control
FIFO
Register
6x
EOC
FD
CS
WR
RD
Data
Input/Output
16
RESET
BYTE
CLK
CH A0
CH A0+
CH A1
CH A1+
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
CH B0
CH B0+
HOLDA
CH B1
CH B1+
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
CH C0
CH C0+
CH C1
CH C1+
REF
IN
REF
OUT
SAR
CDAC
S/H
Amp
Comp
CDAC
Comp
S/H
Amp
HOLDB
HOLDC
ADD
A2
A1
A0
Internal
2.5V
Reference
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
All trademarks are the property of their respective owners.
background image
ADS8364
2
SBAS219B
www.ti.com
MAXIMUM
INTEGRAL
NO MISSING
SPECIFIED
LINEARITY
CODES
PACKAGE
TEMPERATURE
ORDERING
TRANSPORT
PRODUCT
ERROR (LSB)
ERROR (LSB)
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
NUMBER
MEDIA, QUANTITY
ADS8364Y
8
14
TQFP-64
PAG
40
C to +85
C
ADS8364Y/250
Tape and Reel, 250
"
"
"
"
"
"
ADS8364Y/2K
Tape and Reel, 2000
NOTES: (1) For the most current specifications and package information, refer to our website at www.ti.com.
PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless
otherwise noted)
(1)
Supply Voltage, AGND to AV
DD ...............................................................
0.3V to 6V
Supply Voltage, BGND to BV
DD ...............................................................
0.3V to 6V
Supply Voltage, DGND to DV
DD ..............................................................
0.3V to 6V
Analog Input Voltage Range ..................... AGND 0.3V to AV
DD
+ 0.3V
Reference Input Voltage ........................... AGND 0.3V to AV
DD
+ 0.3V
Digital Input Voltage Range ...................... BGND 0.3V to BV
DD
+ 0.3V
Ground Voltage Differences, AGND to BGND/DGND .....................
0.3V
Voltage Differences, BV
DD
, DV
DD
to AGND .......................... 0.3V to 6V
Input Current ot Any Pin Except Supply ......................... 20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, T
J
........ 40
C to 150
C
Operating Free-Air Temperature Range, T
A
...................... 40
C to 85
C
Storage Temperature Range, T
STG
.................................. 65
C to 150
C
Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260
C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under "recommended operating conditions" is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply Voltage, AGND to AV
DD
4.75
5
5.25
V
Supply Voltage, BGND to BV
DD
Low-Voltage Levels
2.7
3.6
V
5V Logic Levels
4.5
5
5.5
V
Supply Voltage, DGND to DV
DD
4.75
5
5.25
V
Difference AV
DD
to DV
DD
0.3
0
0.3
V
Reference Input Voltage
1.5
2.5
2.6
V
Operating Common-Mode Signal
IN
2.2
2.5
2.8
V
Analog Inputs
+IN (IN)
0
V
REF
V
Operating Junction Temperature Range, T
J
40
125
C
DERATING
FACTOR
T
A
25
C
T
A
= 70
C
T
A
= 85
C
ABOVE
POWER
POWER
POWER
BOARD
PACKAGE
R
JC
R
JA
T
A
= 25
C
RATING
RATING
RATING
Low-K
(1)
DGK
8.6
C/W
68.5
C/W
14.598mW/
C
1824mW
1168mW
949mW
High-K
(2)
DGK
8.6
C/W
42.8
C/W
23.364mw/
C
2920mW
1869mW
1519mW
NOTES: (1) The JEDEC Low K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC High K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce
copper traces on the top and bottom of the board.
PACKAGE DISSIPATION RATING TABLE
R
ON
= 20
C
(SAMPLE)
= 20pF
BV
DD
D
IN
BGND
AV
DD
A
IN
AGND
Diode Turn-on Voltage: 0.35V
Equivalent Digital Input Circuit
Equivalent Analog Input Circuit
EQUIVALENT INPUT CIRCUIT
background image
ADS8364
3
SBAS219B
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at 40
C to 85
C, AV
DD
= DV
DD
= 5V, BV
DD
= 3V, V
REF
= internal +2.5V, f
CLK
= 5MHz, f
SAMPLE
= 250kSPS,
unless otherwise noted.
ADS8364Y
PARAMETER
CONDITIONS
MIN
TYP
(1)
MAX
UNITS
ANALOG INPUT
Full-Scale Range
(FSR)
+IN (IN)
V
REF
V
Operating Common-Mode Signal
2.2
2.8
V
Input Resistance
IN = V
REF
20
Input Capacitance
IN = V
REF
25
pF
Input Leakage Current
IN = V
REF
1
nA
Differential Input Resistance
IN = V
REF
40
Differential Input Capacitance
IN = V
REF
50
pF
Common-Mode Rejection Ratio
(CMRR)
At DC
84
dB
V
IN
=
1.25V
PP
at 50kHz
80
dB
Bandwith
(BW)
FS Sinewave, 3dB
300
MHz
DC ACCURACY
Resolution
16
Bits
No Missing Codes
(NMC)
14
Bits
Integral Linearity Error
(INL)
3
8
LSB
Integral Linearity Match
Only pair wise matching
1.5
LSB
Differential Nonlinearity
(DNL)
Specified only for 14-Bit
1.5
LSB
Bipolar Offset Error
(V
OS
)
0.05
2
mV
Bipolar Offset Error Match
Only pair wise matching
0.2
1
mV
Bipolar Offset Error Drift
(TCV
OS
)
0.8
ppm/
C
Gain Error
(G
ERR
)
Referenced to V
REF
0.05
0.25
%FSR
Gain Error Match
Only pair wise matching
0.005
0.05
%FSR
Gain Error Drift
(TCG
ERR
)
2
ppm/
C
Noise
120
V
RMS
Power-Supply Rejection Ratio
(PSRR)
4.75V < AV
DD
< 5.25V
87
dB
SAMPLING DYNAMICS
Conversion Time per ADC
(t
CONV
)
50kHz
f
CLK
5MHz
3.2
320
s
Acquisition Time
(t
AQ
)
f
CLK
= 5MHz
800
ns
Throughput Rate
250
kSPS
Aperture Delay
5
ns
Aperture Delay Matching
100
ps
Aperture Jitter
50
ps
Clock Frequncy
0.05
5
MHz
AC ACCURACY
Total Harmonic Distortion
(THD)
V
IN
=
2.5V
PP
at 100kHz
92
dB
Spurous-Free Dynamic Range
(SFDR)
V
IN
=
2.5V
PP
at 100kHz
93.5
dB
Signal-to-Noise Ratio
(SNR)
V
IN
=
2.5V
PP
at 100kHz
83.2
dB
Signal-to-Noise Ratio + Distortion
(SINAD)
V
IN
=
2.5V
PP
at 100kHz
82.5
dB
Channel-to-Channel Isolation
V
IN
=
2.5V
PP
at 50kHz
95
dB
Effective Number of Bits
(ENOB)
13.3
Bits
VOLTAGE REFERENCE OUTPUT
Reference Voltage Output
(V
OUT
)
2.475
2.5
2.525
V
Initial Accuracy
1
%
Output Voltage Temperature Drift
(dV
OUT
/dT)
20
ppm/
C
Output Voltage Noise
f = 0.1Hz to 10Hz, C
L
= 10
F
40
V
PP
f = 10Hz to 10kHz, C
L
= 10
F
8
VRMS
Power-Supply Refection Ratio
(PSRR)
60
dB
Output Current
(I
OUT
)
10
A
Short-Circuit Current
(I
SC
)
0.5
mA
Turn-On Settling Time
to 0.1% at C
L
= 0
100
s
VOLTAGE REFERENCE INPUT
Reference Voltage Input
(V
IN
)
1.5
2.5
2.6
V
Reference Input Resistance
100
M
Reference Input Capacitance
5
pF
Reference Input Current
1
A
NOTE: (1) All values are at T
A
= 25
C.
background image
ADS8364
4
SBAS219B
www.ti.com
ELECTRICAL CHARACTERISTICS
(Cont.)
Over recommended operating free-air temperature range at 40
C to 85
C, AV
DD
= DV
DD
= 5V, V
REF
= internal +2.5V, f
CLK
= 5MHz, f
SAMPLE
= 250kSPS, unless
otherwise noted.
ADS8364Y
PARAMETER
CONDITIONS
MIN
TYP
(1)
MAX
UNITS
DIGITAL INPUTS
(2)
Logic Family
CMOS
High-Level Input Voltage
(V
IH
)
0.7 BV
DD
BV
DD
+ 0.3
V
Low-Level Input Voltage
(V
IL
)
0.3
0.3 BV
DD
V
Input Current
(I
IN
)
V
I
= BV
DD
or GND
50
nA
Input Capacitance
(C
I
)
5
pF
DIGITAL OUTPUTS
(2)
Logic Family
CMOS
High-Level Output Voltage
(V
OH
)
BV
DD
= 4.5V, I
OH
= 100
A
4.44
V
Low-Level Output Voltage
(V
OL
)
BV
DD
= 4.5V, I
OL
= 100
A
0.5
V
High-Impedance-State Output Current
(I
OZ
)
CS = BV
DD
, V
I
= BV
DD
or GND
50
nA
Output Capacitance
(C
O
)
5
pF
Load Capacitance
(C
L
)
30
pF
Data Format
Binary Two's Complement
DIGITAL INPUTS
(3)
Logic Family
LVCMOS
High-Level Input Voltage
(V
IH
)
BV
DD
= 3.6V
2
BV
DD
+ 0.3
V
Low-Level Input Voltage
(V
IL
)
BV
DD
= 2.7V
0.3
0.8
V
Input Current
(I
IN
)
V
I
= BV
DD
or GND
50
nA
Input Capacitance
(C
I
)
5
pF
DIGITAL OUTPUTS
(3)
Logic Family
LVCMOS
High-Level Output Voltage
(V
OH
)
BV
DD
= 2.7V, I
OH
= 100
A
BV
DD
0.2
V
Low-Level Output Voltage
(V
OL
)
BV
DD
= 2.7V, I
OL
= 100
A
0.2
V
High-Impedance-State Output Current
(I
OZ
)
CS = BV
DD
, VI = BV
DD
or GND
50
nA
Output Capacitance
(C
O
)
5
pF
Load Capacitance
(C
L
)
30
pF
Data Format
Binary Two's Complement
POWER SUPPLY
Analog Supply Voltage
(AV
DD
)
4.75
5.25
V
Buffer I/O Supply Voltage
(BV
DD
)
Low-Voltage Levels
2.7
3.6
V
5V Logic Levels
4.5
5.5
V
Digital Supply Voltage
(DV
DD
)
4.75
5.25
V
Analog Operating Supply Current
(AI
DD
)
80
90
mA
Buffer I/O Operating Supply Current
(BI
DD
)
BV
DD
= 3V
300
A
BV
DD
= 5V
200
300
A
Digital Operating Supply Current
(DI
DD
)
2.5
4
mA
Power Dissipation
BV
DD
= 3V
413.1
470.9
mW
BV
DD
= 5V
413.5
471.5
mW
NOTES: (1) All values are at T
A
= 25
C. (2) Applies for 5.0V nominal Supply: BV
DD
(min) = 4.5V and BV
DD
(max) = 5.5V. (3) Applies for 3.0V nominal Supply:
BV
DD
(min) = 2.7V and BV
DD
(max) = 3.6V.
background image
ADS8364
5
SBAS219B
www.ti.com
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CH A1
CH A1+
AV
DD
AGND
SGND
CH B0+
CH B0
AV
DD
AGND
SGND
CH B1
CH B1+
AV
DD
AGND
SGND
CH C0+
CH A0
CH A0+
REF
IN
REF
OUT
AGND
AV
DD
HOLD C
HOLD B
HOLD A
A0
A1
A2
ADD
RESET
BV
DD
BGND
CH C0
CH C1
CH C1+
NC
DGND
DV
DD
BYTE
BV
DD
BGND
FD
EOC
CLK
RD
WR
CS
BGND
64
63
62
61
60
59
58
57
56
55
54
17
18
19
20
21
22
23
24
25
26
27
53
52
51
50
49
28
29
30
31
32
ADS8364
PIN CONFIGURATION
1
CH A1
AI
Inverting Input Channel A1
2
CH A1+
AI
Noninverting Input channel A1
3
AV
DD
P
Analog Power Supply
4
AGND
P
Analog Ground
5
SGND
P
Signal Ground
6
CH B0+
AI
Noninverting Input Channel B0
7
CH B0
AI
Inverting Input Channel B0
8
AV
DD
P
Analog Power Supply
9
AGND
P
Analog Ground
10
SGND
P
Signal Ground
11
CH B1
AI
Inverting Input Channel B1
12
CH B1+
AI
Noninverting Input Channel B1
13
AV
DD
P
Analog Power Supply
14
AGND
P
Analog Ground
15
SGND
P
Signal Ground
16
CH C0+
AI
Noninverting Input Channel C0
17
CH C0
AI
Inverting Input Channel C0
18
CH C1
AI
Inverting Input Channel C1
19
CH C1+
AI
Noninverting Input Channel C1
20
NC
No Connection
21
DGND
P
Digital ground connected to AGND.
22
DV
DD
P
+5V Power Supply for Digital Logic Connected to AV
DD
.
23
BYTE
DI
2 x 8 Output Capability. Active HIGH.
24
BV
DD
P
Power supply for digital interface from 3V to 5V.
25
BGND
P
Buffer Digital Ground
26
FD
DO
First Data, A0 Data
27
EOC
DO
End of Conversion, Active LOW
28
CLK
DI
An external CMOS compatible clock can be applied to
the CLK input to synchronize the conversion process to
an external source.
29
RD
DI
Read, Active LOW
30
WR
DI
Write, Active LOW
31
CS
DI
Chip Select, Active LOW
32
BGND
P
Buffer Digital Ground
33
DB15
DO
Data Bit 15-MSB
34
DB14
DO
Data Bit 14
35
DB13
DO
Data Bit 13
36
DB12
DO
Data Bit 12
37
DB11
DO
Data Bit 11
38
DB10
DO
Data Bit 10
39
DB9
DO
Data Bit 9
40
DB8
DO
Data Bit 8
41
DB7
DIO
Data Bit 7, Software Input 7
42
DB6
DIO
Data Bit 6, Software Input 6
43
DB5
DIO
Data Bit 5, Software Input 5
44
DB4
DIO
Data Bit 4, Software Input 4
45
DB3
DIO
Data Bit 3, Software Input 3
46
DB2
DIO
Data Bit 2, Software Input 2
47
DB1
DIO
Data Bit 1, Software Input 1
48
DB0
DIO
Data Bit 0, Software Input 0
49
BGND
P
Buffer Digital Ground
50
BV
DD
P
Power Supply for Digital Interface from 3V to 5V
51
RESET
DI
Global Reset, Active LOW
52
ADD
DI
Address Mode Select
53
A2
DI
Address Line 3
54
A1
DI
Address Line 2
55
A0
DI
Address Line 1
56
HOLDA
DI
Hold Command A
57
HOLDB
DI
Hold Command B
58
HOLDC
DI
Hold Command C
59
AV
DD
P
Analog Power Supply
60
AGND
P
Analog Ground
61
REF
OUT
AO
Reference Output, attach 0.1
F and 10
F capacitors.
62
REF
IN
AI
Reference Input
63
CH A0+
AI
Noninverting Input Channel A0
64
CH A0
AI
Inverting Input Channel A0
PIN
NAME
I/O
DESCRIPTION
PIN
NAME
I/O
DESCRIPTION
PIN DESCRIPTIONS
NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, DIO is Digital Input/Output, P is Power Supply Connection.

Document Outline