1
Features
ACPI-compliant day-of-month
alarm
Y2K century bit
Direct clock/calendar replace-
ment for IBM
AT-compatible
computers and other applications
2 index shadow registers
2.75.5V operation
240 bytes of general nonvolatile
storage
Dedicated 32.768kHz output pin
System wake-up capability--
alarm interrupt output active in
battery-backup mode
Less than 0.55
A load under bat-
tery operation
Selectable Intel or Motorola bus
timing
24-pin plastic SSOP
General Description
The CMOS bq3285LF is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal-
endar with alarm features and bat-
tery operation. The architecture is
based on the bq3285 RTC with added
features: century bit, low-voltage op-
eration, 32.768kHz output, 126 addi-
tional bytes of CMOS, two shadow
registers of last address used, and a
day-of-month alarm to be compliant
with the ACPI RTC specification.
A 32.768kHz output is available for
sustaining power-management ac-
tivities. The bq3285LF 32kHz out-
put is always on whenever V
CC
is
valid. In V
CC
standby mode, the
32kHz is active, and the bq3285LF
typically draws 100
A. Wake-up ca-
pability is provided by an alarm in-
terrupt, which is active in battery-
backup mode. In battery-backup
mode, current drain is less than
550nA.
The bq3285LF write-protects the
clock, calendar, and storage registers
during power failure.
A backup
battery then maintains data and oper-
ates the clock and calendar.
The bq3285LF is a fully compatible
real-time
clock
for
IBM
AT-
compatible computers and other ap-
plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
The bq3285LF is intended for use in
3V systems; however, it may also op-
erate at 5V and then go into a 3V
power-down state, write-protecting
as if in a 3V system.
Y2K-Enhanced
Real-Time Clock (RTC)
bq3285LF
1
PN3285ED/LD.eps
24-Pin SSOP
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
16
15
11
12
14
13
VCC
32k
EXTRAM
BC
INT
RST
DS
VSS
R/W
AS
CS
MOT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
RCL
Pin Connections
Pin Names
6/99 B
AD
0
AD
7
Multiplexed address/
data input/output
MOT
Bus type select input
CS
Chip select input
AS
Address strobe input
DS
Data strobe input
R/W
Read/write input
INT
Interrupt request output
RST
Reset input
32K
32.768kHz output
EXTRAM
Extended RAM enable
RCL
RAM clear input
BC
3V backup cell input
X1X2
Crystal inputs
V
CC
Supply voltage input
V
SS
Ground
Block Diagram
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture.
This pin should be
tied to V
CC
for Motorola timing or to V
SS
for
Intel timing (see Table 1).
The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
resistor.
AD
0
AD
7
Multiplexed address/data
input/output
The bq3285LF bus cycle consists of two
p h a s e s : t h e a d d r e s s p h a s e a n d t h e
data-transfer phase.
The address phase
precedes the data-transfer phase.
During
the address phase, an address placed on
AD
0
AD
7
is latched into the bq3285LF on
the falling edge of the AS signal. During
the data-transfer phase of the bus cycle, the
AD0AD
7
pins serve as a bidirectional data
bus.
AS
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD
0
AD
7
. This demultiplexing pro-
cess is independent of the CS signal. For
DIP and SOIC packages with MOT = V
SS
,
the AS input is provided a signal similar to
ALE in an Intel-based system.
2
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Motorola
V
CC
DS, E, or
2
R/W
AS
Intel
V
SS
RD,
MEMR, or
I/OR
WR,
MEMW, or
I/OW
ALE
Table 1. Bus Setup
BD3285ID.eps
P
Bus
I/F
Power-
Fail
Control
Storage Registers
(114 Bytes)
User Buffer
(14 Bytes)
VOUT
Clock/Calendar, Alarm
and Control Bytes
Time-
Base
Oscillator
Control/Status
Registers
8
64
64
16 1 MUX
:
Interupt
Generator
Control/Calendar
Update
VCC
DS
AD0AD7
CS
MOT
32K
INT
X1
X2
3
4
RST
R/W
AS
Storage Registers
(126 Bytes)
Index Registers
(2 Bytes)
RCL
EXTRAM
Write
Protect
CS
BC
32K
Driver
MUX
bq3285LF
A low input on EXTRAM during the falling
e d g e o f A S l a t ch e s t h e a d d r e s s i n t o
standard bank address latch. A high input
on the EXTRAM input during the falling
edge of AS latches the address into the
extended bank address latch. The contents
of the address latches are copied into the
standard bank index and the extended bank
index registers respectively. EXTRAM is not
latched.
DS
Data strobe input
When MOT = V
CC
, DS controls data trans-
fer during a bq3285LF bus cycle. During a
read cycle, the bq3285LF drives the bus af-
ter the rising edge on DS. During a write
cycle, the falling edge on DS is used to latch
write data into the chip.
When MOT = V
SS
, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
The state of the EXTRAM input selects the
address latch used during data access. A
low input on EXTRAM selects the standard
bank latch and the location in the standard
bank pointed to by the value in this latch. A
high input on the EXTRAM selects the ex-
tended bank latch and the location in the
extended bank pointed to by the value in
this latch.
R/W
Read/write input
When MOT = V
CC
, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = V
SS
, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system.
The rising edge on R/W
latches data into the bq3285LF.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285LF.
INT
Interrupt request output
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than V
CC
. INT is asserted low when any
event flag is set and the corresponding event
enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
32K
32.768 kHz output
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as V
CC
is valid.
EXTRAM
Extended RAM enable
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30k
pull-down resistor. To access the RTC reg-
isters, EXTRAM must be low.
The input on this pin also selects the latch
to be used in the data transfer. A low value
selects the standard bank latch. A high
value selects the extended the bank latch.
EXTRAM should be valid for complete ad-
dress, read or write cycle.
RCL
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 240 storage bytes to be
set to FF(hex). RCL clears the shadow in-
dex registers to 00(hex). The contents of the
clock and control registers are unaffected.
This pin should be used as a user-interface
input (pushbutton to ground) and not con-
nected to the output of any active compo-
nent. RCL input is only recognized when
held low for at least 125ms in the presence
of V
CC
. Using RAM clear does not affect the
battery load. This pin is connected inter-
nally to a 30k
pull-up resistor.
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register
nonvolatility in the absence of system power.
When V
CC
slews down past V
BC
(3V typical),
the integral control circuitry switches the
power source to BC. When V
CC
returns above
V
BC
, the power source is switched to V
CC
.
On power-up, a voltage within the V
BC
range must be present on the BC pin for
the oscillator to start up.
3
bq3285LF
RST
Reset input
The bq3285LF is reset when RST is pulled
low. When reset, INT becomes high impedance,
and the bq3285LF is not accessible. Table 4 in
the Control/Status Registers section lists the
register bits that are cleared by a reset.
Reset may be disabled by connecting RST to
V
CC
. This allows the control bits to retain
their states through power-down/power-up
cycles.
X1X2
Crystal inputs
The X1X2 inputs are provided for an exter-
nal 32.768kHz quartz crystal, Daiwa DT-26
or equivalent, with 6pF load capacitance. A
trimming capacitor may be necessary for
extremely precise time-base generation.
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
Functional Description
Address Map
The bq3285LF provides 14 bytes of clock and con-
trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285LF.
Update Period
The update period for the bq3285LF is one second. The
bq3285LF updates the contents of the clock and calen-
dar locations during the update cycle at the end of each
update period (see Figure 2). The alarm flag bit may
also be set during the update cycle.
The bq3285LF copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in regis-
ter B, the user copy of the clock and calendar bytes re-
4
FG3285ID.eps
Clock and
Control Status
Registers
00
0D
0E
7F
00
7D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of Week
Date of Month
Month
Year
Register A
Register B
Register C
Day of Month
Alarm
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
Storage
Registers
with
EXTRAM = 1
Index
Registers
Standard Index Register
Extended Index Register
plus Century bit
14 Bytes
0
13
14
127
0
125
Storage
Registers
with
EXTRAM = 0
126
Bytes
2
Bytes
114
Bytes
BCD
or
Binary
Format
127
126
7E
7F
Figure 1. Address Map
Update Period
(1 sec.)
TD3285e1.eps
t
UC
(Update Cycle)
t
BUC
UIP
Figure 2. Update Period Timing and UIP
bq3285LF
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
The update-in-progress bit (UIP) in register A is set t
BUC
time before the beginning of an update cycle (see Figure
2). This bit is cleared and the update-complete flag (UF)
is set at the end of the update cycle.
Programming the RTC
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
These steps may be followed to program the time, alarm,
and calendar:
1.
Modify the contents of register B:
a.
Write a 1 to the UTI bit to prevent trans-
fers between RTC bytes and user buffer.
b.
Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
2.
Write new values to all the time, alarm, and
calendar locations.
3.
The CENT bit in location 7Fh (bit 7) of the ex-
tended SRAM bank is read only. Writing year
in location 09h automatically updates CENT.
4.
Clear the UTI bit to allow update transfers.
5
Address
RTC Bytes
Range
Decimal
Binary
Binary-Coded
Decimal
0
Seconds
059
00H3BH
00H59H
1
Seconds alarm
059
00H3BH
00H59H
2
Minutes
059
00H3BH
00H59H
3
Minutes alarm
059
00H3BH
00H59H
4
Hours, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours, 24-hour format
023
00H17H
00H23H
5
Hours alarm, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours alarm, 24-hour format
023
00H17H
00H23H
6
Day of week (1=Sunday)
17
01H07H
01H07H
7
Day of month
131
01H1FH
01H31H
8
Month
112
01H0CH
01H12H
9
Year (see note)
099
00H63H
00H99H
D
Day of month alarm
131
01H-1FH
0131H
Note:
Century for "Year" is shown in location 7Fh (Extended Index Register, bit 7) .
Table 2. Time, Alarm, Calendar, and Index Formats
bq3285LF
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