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Электронный компонент: BQ3285P-

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Features
Direct clock/calendar replace-
ment for IBM
AT-compatible
computers and other applications
Functionally compatible with the
DS1285
-
Closely matches MC146818A
pin configuration
114 bytes of general nonvolatile
storage
160ns cycle time allows fast bus
operation
Selectable Intel or Motorola bus
timing
Less than 0.5
A load under bat-
tery operation
14 bytes for clock/calendar and
control
BCD or binary format for clock
and calendar data
Calendar in day of the week, day
of the month, months, and years,
with automatic leap-year adjust-
ment
Time of day in seconds, minutes,
and hours
-
12- or 24-hour format
-
Optional daylight saving
adjustment
Programmable square wave out-
put
Three individually maskable in-
terrupt event flags:
-
Periodic rates from 122
s to
500ms
-
Time-of-day alarm once per
second to once per day
-
End-of-clock update cycle
24-pin plastic DIP or SOIC
General Description
The CMOS bq3285 is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal-
endar with alarm features and bat-
tery operation. Other features in-
clude three maskable interrupt
sources, square wave output, and 114
bytes of general nonvolatile storage.
The bq3285 write-protects the clock,
calendar, and storage registers during
power failure.
A backup battery
then maintains data and operates the
clock and calendar.
The bq3285 is a fully compatible
real-time clock for IBM AT com-
patible computers and other appli-
cations. The only external compo-
nents are a 32.768kHz crystal and
a backup battery
1
bq3285
Real-Time Clock (RTC)
PN328501.eps
28-Pin PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2
1
28
27
26
12
13
14
15
16
17
18
AD0
AD1
AD2
AD3
AD4
AD5
NC
AD
6
NC
AD
7
V
SS
CS
AS
NC
RCL
BC
INT
RST
DS
VSS
R/ W
X2
X1
MOT
NC
V
CC
SQW
NC
Pin Names
AD
0
AD
7
Multiplexed address/data
input/output
MOT
Bus type select input
CS
Chip select input
AS
Address strobe input
DS
Data strobe input
R/W
Read/write input
INT
Interrupt request
output
RST
Reset input
SQW
Square wave output
RCL
RAM clear input
BC
3V backup cell input
X1X2
Crystal inputs
NC
No connect
V
CC
+5V supply
V
SS
Ground
1
PN328501.eps
24-Pin DIP or SOIC
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
16
15
11
12
14
13
VCC
SQW
NC
BC
INT
RST
DS
VSS
R/W
AS
CS
MOT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
RCL
Pin Connections
Jan. 1999 E
Block Diagram
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture.
This pin should be
tied to V
CC
for Motorola timing or to V
SS
for
Intel timing (see Table 1).
The setting
should not be changed during system opera-
tion.
MOT is internally pulled low by a
30K
resistor.
AD
0
AD
7
Multiplexed address/data input/
output
The bq3285 bus cycle consists of two
phases: the address phase and the data-
transfer phase.
The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD
0
AD
7
is latched into the bq3285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD
0
AD
7
pins serve as a bidirectional data
bus.
AS
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD
0
AD
7
. This demultiplexing pro-
cess is independent of the CS signal.
For
DIP, SOIC, and PLCC packages with MOT =
V
CC
, the AS input is provided a signal simi-
lar to ALE in an Intel-based system.
2
Jan. 1999 E
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Motorola
V
CC
DS, E, or
2
R/W
AS
Intel
V
SS
RD,
MEMR, or
I/OR
WR,
MEMW, or
I/OW
ALE
Table 1. Bus Setup
bq3285
DS
Data strobe input
When MOT = V
CC
, DS controls data trans-
fer during a bq3285 bus cycle.
During a
read cycle, the bq3285 drives the bus after
the rising edge on DS. During a write cycle,
the falling edge on DS is used to latch write
data into the chip.
When MOT = V
SS
, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
R/W
Read/write input
When MOT = V
CC
, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = V
SS
, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system.
The rising edge on R/W
latches data into the bq3285.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285.
INT
Interrupt request output
INT is an open-drain output.
INT is as-
serted low when any event flag is set and
the corresponding event enable bit is also
set. INT becomes high-impedance whenever
register C is read (see the Control/Status
Registers section).
SQW
Square-wave output
SQW may output a programmable fre-
quency square-wave signal during normal
(V
CC
valid) system operation.
Any one of
the 13 specific frequencies may be selected
through register A.
This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).
RCL
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 114 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of V
CC
when
the oscillator is running. Using RAM clear
does not affect the battery load. This pin is
connected internally to a 30K
pull-up re-
sistor.
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of power.
When
V
CC
slews down past V
BC
(3V typical), the
integral control circuitry switches the
power source to BC.
When V
CC
returns
above V
BC
, the power source is switched to
V
CC
.
Upon power-up, a voltage within the V
BC
range must be present on the BC pin for
the oscillator to start up.
RST
Reset input
The bq3285 is reset when RST is pulled low.
When reset, INT becomes high-impedance,
and the bq3285 is not accessible. Table 4 in
the Control/Status Registers section lists
the register bits that are cleared by a reset.
Reset may be disabled by connecting RST
to V
CC
. This allows the control bits to re-
t a i n
t h e i r
s t a t e s
t h r o u g h
p o w e r-
down/power-up cycles.
X1X2
Crystal inputs
The X1X2 inputs are provided for an ex-
ternal 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
In the absence of a crystal, an oscillated
output of 32.768kHz can be fed into the X1
input.
3
Jan. 1999 E
bq3285
Functional Description
Address Map
The bq3285 provides 14 bytes of clock and control/status
registers and 114 bytes of general nonvolatile storage.
Figure 1 illustrates the address map for the bq3285.
Update Period
The update period for the bq3285 is one second. The
bq3285 updates the contents of the clock and calendar
locations during the update cycle at the end of each up-
date period (see Figure 2). The alarm flag bit may also
be set during the update cycle.
The bq3285 copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in regis-
ter B, the user copy of the clock and calendar bytes re-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
The update-in-progress bit (UIP) in register A is set
t
BUC
time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
4
Clock and
Control Status
Registers
Storage
Registers
14
Bytes
114
Bytes
00
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
13
14
127
7F
0E
0D
BCD or
Binary
Format
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Month
Year
Register A
Register B
Register C
Register D
Hours Alarm
Day of Week
Day of Month
Figure 1. Address Map
Update Period
(1s)
t
BUC
tUC (Update Cycle)
UIP
Figure 2. Update Period Timing and UIP
Jan. 1999 E
bq3285
Programming the RTC
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
These steps may be followed to program the time, alarm,
and calendar:
1.
Modify the contents of register B:
a.
Write a 1 to the UTI bit to prevent trans-
fers between RTC bytes and user buffer.
b.
Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
2.
Write new values to all the time, alarm, and
calendar locations.
3.
Clear the UTI bit to allow update transfers.
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
5
Address
RTC Bytes
Range
Decimal
Binary
Binary-Coded Decimal
0
Seconds
059
00H3BH
00H59H
1
Seconds alarm
059
00H3BH
00H59H
2
Minutes
059
00H3BH
00H59H
3
Minutes alarm
059
00H3BH
00H59H
4
Hours, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours, 24-hour format
023
00H17H
00H23H
5
Hours alarm, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours alarm, 24-hour format
023
00H17H
00H23H
6
Day of week (1=Sunday)
17
01H07H
01H07H
7
Day of month
131
01H1FH
01H31H
8
Month
112
01H0CH
01H12H
9
Year
099
00H63H
00H99H
Table 2. Time, Alarm, and Calendar Formats
Jan. 1999 E
bq3285