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Электронный компонент: BQ4285

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1
Features
Direct clock/calendar replace-
ment for IBM
AT-compatible
computers and other applications
Functionally compatible with the
DS1285
-
Closely matches MC146818A
pin configuration
114 bytes of general nonvolatile
storage
Automatic backup and write-
protect control to external SRAM
160 ns cycle time allows fast bus
operation
Less than 0.5
A load under bat-
tery operation
14 bytes for clock/calendar and
control
Calendar in day of the week, day of
the month, months, and years, with
automatic leap-year adjustment
Time of day in seconds, minutes,
and hours
-
12- or 24-hour format
-
Optional daylight saving
adjustment
BCD or binary format for clock
and calendar data
Programmable square wave out-
put
Three individually maskable in-
terrupt event flags:
-
Periodic rates from 122
s to
500 ms
-
Time-of-day alarm once per
second to once per day
-
End-of-clock update cycle
24-pin plastic DIP or SOIC
General Description
The CMOS bq4285 is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal-
endar with alarm features and bat-
tery operation. Other features include
three maskable interrupt sources,
square wave output, and 114 bytes of
general nonvolatile storage.
The bq4285 write-protects the clock,
calendar, and storage registers dur-
ing power failure. A backup battery
then maintains data and operates
the clock and calendar.
The bq4285 is a fully compatible real-
time clock for IBM AT-compatible com-
puters and other applications. The only
external components are a 32.768kHz
crystal and a backup battery.
The bq4285 integrates a battery-
backup controller to make a standard
CMOS SRAM nonvolatile during
power-fail conditions. During power-
fail, the bq4285 automatically write-
protects the external SRAM and pro-
vides a V
CC
output sourced from the
clock backup battery.
28-Pin PLCC
No longer available
Pin Names
AD
0
AD
7
Multiplexed address/data
input/output
MOT
Bus type select input
CS
Chip select input
AS
Address strobe input
DS
Data strobe input
R/W
Read/write input
INT
Interrupt request output
RST
Reset input
SQW
Square wave output
BC
3V backup cell input
X1X2
Crystal inputs
NC
No connect
CE
IN
RAM chip enable input
CE
OUT
RAM chip enable output
V
OUT
Supply output
V
CC
+5V supply
V
SS
Ground
SLUS002A JUNE 1991 - REVISED MAY 2004
1
PN428501.eps
24-Pin DIP or SOIC
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
16
15
11
12
14
13
VCC
SQW
CEOUT
BC
INT
RST
DS
VSS
R/W
AS
CS
VOUT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
CEIN
Pin Connections
bq4285
Real-Time Clock (RTC) With NVRAM Control
Block Diagram
Pin Descriptions
AD
0
AD
7
Multiplexed address/data input/
output
The bq4285 bus cycle consists of two
phases: the address phase and the data-
transfer phase.
The address phase pre-
cedes the data-transfer phase. During the
address
phase,
an
address
placed
on
AD
0
AD
7
is latched into the bq4285 on the
falling edge of the AS signal.
During the
data-transfer phase of the bus cycle, the
AD
0
AD
7
pins serve as a bidirectional data
bus.
MOT
Connect to VSS for correct operation
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq4285.
2
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Intel
V
SS
RD,
MEMR,
or I/OR
WR,
MEMW,
or I/OW
ALE
Table 1. Bus Setup
bq4285
AS
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD
0
AD
7
.
This demultiplexing
process is independent of the CS signal.
DS
Data strobe input
With MOT = V
SS
, the DS input is provided a sig-
nal similar to RD, MEMR, or I/OR in an
Intel-based system. The falling edge on DS
is used to enable the outputs during a read
cycle.
R/W
Read/write input
With MOT = V
SS
, R/W is provided a signal simi-
lar to WR, MEMW, or I/OW in an Intel-
based system.
The rising edge on R/W
latches data into the bq4285.
INT
Interrupt request output
INT is an open-drain output.
INT is as-
serted low when any event flag is set and
the corresponding event enable bit is also
set.
INT
becomes
high-impedance
whenever register C is read (see the Con-
trol/Status Registers section).
RST
Reset input
The bq4285 is reset when RST is pulled
low.
When reset, INT becomes high-
impedance, and the bq4285 is not accessi-
ble. Table 4 in the Control/Status Registers
section lists the register bits that are
cleared by a reset.
Reset may be disabled by connecting RST
to V
CC
. This allows the control bits to re-
tain
their
states
through
power-
down/power-up cycles.
SQW
Square-wave output
SQW may output a programmable fre-
quency square-wave signal during normal
(V
CC
valid) system operation.
Any one of
the 13 specific frequencies may be selected
through register A.
This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of power.
When
V
CC
slews down past V
BC
(3V typical), the
integral
control
circuitry
switches
the
power source to BC.
When V
CC
returns
above V
BC
, the power source is switched to
V
CC
.
Upon power-up, a voltage within the V
BC
range must be present on the BC pin for
the oscillator to start up.
X1X2
Crystal inputs
The X1X2 inputs are provided for an ex-
ternal 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
CE
IN
External RAM chip enable input,
active low
CE
IN
should be driven low to enable the
controlled external RAM. CE
IN
is internally
pulled up with a 50K
resistor.
CE
OUT
External RAM chip enable output,
active low
When power is valid, CE
OUT
reflects CE
IN.
V
OUT
Supply output
V
OUT
provides the higher of V
CC
or V
BC
,
switched internally, to supply external RAM.
V
CC
+5V supply
V
SS
Ground
3
bq4285
Functional Description
Address Map
The bq4285 provides 14 bytes of clock and control/status
registers and 114 bytes of general nonvolatile storage.
Figure 1 illustrates the address map for the bq4285.
Update Period
The update period for the bq4285 is one second. The
bq4285 updates the contents of the clock and calendar
locations during the update cycle at the end of each up-
date period (see Figure 2). The alarm flag bit may also
be set during the update cycle.
The bq4285 copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in regis-
ter B, the user copy of the clock and calendar bytes re-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
The update-in-progress bit (UIP) in register A is set
t
BUC
time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
4
Figure 1. Address Map
Figure 2. Update Period Timing and UIP
bq4285
Programming the RTC
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
These steps may be followed to program the time, alarm,
and calendar:
1.
Modify the contents of register B:
a.
Write a 1 to the UTI bit to prevent trans-
fers between RTC bytes and user buffer.
b.
Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
2.
Write new values to all the time, alarm, and
calendar locations.
3.
Clear the UTI bit to allow update transfers.
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
5
Address
RTC Bytes
Range
Decimal
Binary
Binary-Coded
Decimal
0
Seconds
059
00H3BH
00H59H
1
Seconds alarm
059
00H3BH
00H59H
2
Minutes
059
00H3BH
00H59H
3
Minutes alarm
059
00H3BH
00H59H
4
Hours, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours, 24-hour format
023
00H17H
00H23H
5
Hours alarm, 12-hour format
112
01HOCH AM;
81H8CH PM
01H12H AM;
81H92H PM
Hours alarm, 24-hour format
023
00H17H
00H23H
6
Day of week (1=Sunday)
17
01H07H
01H07H
7
Day of month
131
01H1FH
01H31H
8
Month
112
01H0CH
01H12H
9
Year
099
00H63H
00H99H
Table 2. Time, Alarm, and Calendar Formats
bq4285