Features
Integrated SRAM, real-time
clock, CPU supervisor, crystal,
power-fail control circuit, and
battery
Real-Time Clock counts hun-
dredths of seconds through years
in BCD format
RAM-like clock access
Compatible with industry-
standard 128K x 8 SRAMs
Unlimited write cycles
10-year minimum data retention
and clock operation in the ab-
sence of power
Automatic power-fail chip dese-
lect and write-protection
Watchdog timer, power-on reset,
alarm/periodic interrupt, power-
fail and battery-low warning
Software clock calibration for
g r e a t e r t h a n
1 m i n u t e p e r
month accuracy
General Description
The bq4842Y RTC Module is a non-
volatile 1,048,576-bit SRAM organ-
ized as 131,072 words by 8 bits with
an integral accessible real-time
clock and CPU supervisor. The CPU
supervisor provides a programmable
watchdog timer and a microproces-
sor reset. Other features include
alarm, power-fail, and periodic inter-
rupts, and a battery-low warning.
The device combines an internal
lithium battery, quartz crystal, clock
and power-fail chip, and a full
CMOS SRAM in a plastic 32-pin
DIP module. The RTC Module di-
rectly replaces industry-standard
SRAMs and also fits into many
E P R O M a n d E E P R O M s o ck e t s
without any requirement for special
write timing or limitations on the
number of write cycles.
Registers for the real-time clock,
alarm and other special
functions
are located in registers 1FFF0h
1FFFFh of the memory array.
The clock and alarm registers are
dual-port read/write SRAM loca-
tions that are updated once per sec-
ond by a clock control circuit from
the internal clock counters.
The
dual-port registers allow clock up-
dates to occur without interrupting
normal access to the rest of the
SRAM array.
The bq4842Y also contains a power-
fail-detect circuit. The circuit dese-
lects the device whenever V
CC
falls
below tolerance, providing a high de-
gree of data security. The battery is
electrically isolated when shipped
from the factory to provide maxi-
mum battery capacity. The battery
remains disconnected until the first
application of V
CC
.
1
bq4842Y
1
PN484201.eps
32-Pin DIP Module
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
9
10
24
23
11
12
22
21
13
14
20
19
15
16
18
17
VCC
A15
INT
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Pin Names
A
0
A
16
Address input
CE
Chip enable
RST
Microprocessor reset
WE
Write enable
OE
Output enable
DQ
0
DQ
7
Data in/data out
INT
Programmable interrupt
V
CC
+5 volts
V
SS
Ground
Sept. 1996 C
Pin Connections
RTC Module With 128Kx8 NVSRAM
Functional Description
Figure 1 is a block diagram of the bq4842Y. The follow-
ing sections describe the bq4842Y functional operation,
including memory and clock interface, data-retention
modes, power-on reset timing, watchdog timer activa-
tion, and interrupt generation.
2
Figure 1. Block Diagram
V
CC
CE
OE
WE
Mode
DQ
Power
< V
CC
(max.)
V
IH
X
X
Deselect
High Z
Standby
V
IL
X
V
IL
Write
D
IN
Active
> V
CC
(min.)
V
IL
V
IL
V
IH
Read
D
OUT
Active
V
IL
V
IH
V
IH
Read
High Z
Active
< V
PFD
(min.) > V
SO
X
X
X
Deselect
High Z
CMOS standby
V
SO
X
X
X
Deselect
High Z
Battery-backup mode
Truth Table
Sept. 1996 C
bq4842Y
Address Map
The bq4842Y provides 16 bytes of clock and control
status registers and 131,056 bytes of storage RAM.
Figure 2 illustrates the address map for the bq4842Y.
Table 1 is a map of the bq4842Y registers, and Table 2
describes the register bits.
Memory Interface
Read Mode
The bq4842Y is in read mode whenever OE (output enable)
is low and CE (chip enable) is low. The device architecture
allows ripple-through access of data from eight of 1,048,576
locations in the static storage array. Thus, the unique ad-
dress specified by the 17 address inputs defines which one
of the 131,072 bytes of data is to be accessed. Valid data is
available at the data I/O pins within t
AA
(address access
time) after the last address input signal is stable, providing
that the CE and OE (output enable) access times are also
satisfied. If the CE and OE access times are not met, valid
data is available after the latter of chip enable access time
(t
ACE
) or output enable access time (t
OE
).
CE and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before t
AA
, the data
lines are driven to an indeterminate state until t
AA
. If the
address inputs are changed while CE and OE remain low,
output data remains valid for t
OH
(output data hold time),
but goes indeterminate until the next address access.
Write Mode
The bq4842Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the latter-
occurring falling edge of WE or CE. A write is terminated
by the earlier rising edge of WE or CE. The addresses
must be held valid throughout the cycle. CE or WE must
return high for a minimum of t
WR2
from CE or t
WR1
from
WE prior to the initiation of another read or write cycle.
Data-in must be valid t
DW
prior to the end of write and re-
main valid for t
DH1
or t
DH2
afterward. OE should be kept
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CE and
OE, a low on WE disables the outputs t
WZ
after WE falls.
Data-Retention Mode
With valid VCC applied, the bq4842Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself t
WPT
after V
CC
falls below V
PFD
.
All outputs become high impedance, and all inputs are
treated as "don't care."
3
FG484201.eps
Clock and
Control Status
Registers
1FFFF
1FFF0
1FFEF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Year
Month
Date
Days
Hours
Minutes
Seconds
Control
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
Tenths/
Hundredths
Flags
1FFFF
1FFFE
1FFFD
1FFFC
1FFFB
1FFFA
1FFF9
1FFF8
1FFF7
1FFF6
1FFF5
1FFF4
1FFF3
1FFF2
1FFF1
1FFF0
Storage
RAM
16 Bytes
131,056
Bytes
0000
Figure 2. Address Map
Sept. 1996 C
bq4842Y
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory cycle
fails to terminate within time t
WPT
, write-protection takes
place.
When V
CC
drops below V
SO
, the control circuit
switches power to the internal energy source, which pre-
serves data.
The internal coin cell maintains data in the bq4842Y after
the initial application of V
CC
for an accumulated period of
at least 10 years when V
CC
is less than V
SO
. As system
power returns and Vcc rises above V
SO
, the battery is dis-
connected, and the power supply is switched to external
V
CC
. Write-protection continues for t
CER
after V
CC
reaches
V
PFD
to allow for processor stabilization. After t
CER
, nor-
mal RAM operation can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4842Y is the same as that for the general-purpose stor-
age memory.
Once every second, the user-accessible
clock/calendar locations are updated simultaneously from
the internal real time counters. To prevent reading data
in transition, updates to the bq4842Y clock registers
should be halted. Updating is halted by setting the read
bit D6 of the control register to 1. As long as the read bit
is 1, updates to user-accessible clock locations are inhib-
ited. Once the frozen clock information is retrieved by
reading the appropriate clock memory locations, the read
bit should be reset to 0 in order to allow updates to occur
from the internal counters. Because the internal coun-
ters are not halted by setting the read bit, reading the
clock locations has no effect on clock accuracy. Once the
read bit is reset to 0, within one second the internal regis-
ters update the user-accessible registers with the correct
time. A halt command issued during a clock update al-
lows the update to occur before freezing the data.
Setting the Clock
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (1FFF1FFF9).
4
Sept. 1996 C
Address
D7
D6
D5
D4
D3
D2
D1
D0
Range (h)
Register
1FFFF
10 Years
Year
0099
Year
1FFFF
X
X
X
10 Month
Month
0112
Month
1FFFD
X
X
10 Date
Date
0131
Date
1FFFC
X
FTE
X
X
X
Day
0107
Days
1FFFB
X
X
10 Hours
Hours
0023
Hours
1FFFA
X
10 Minutes
Minutes
0059
Minutes
1FFF9
OSC
10 Seconds
Seconds
0059
Seconds
1FFF8
W
R
S
Calibration
0031
Control
1FFF7
WDS
BM4
BM3
BM2
BM1
BM0
WD1
WD0
Watchdog
1FFF6
AIE
PWRIE
ABE
PIE
RS3
RS2
RS1
RS0
Interrupts
1FFF5
ALM3
X
10-date alarm
Alarm date
0131
Alarm date
1FFF4
ALM2
X
10-hour alarm
Alarm hours
0023
Alarm hours
1FFF3
ALM1
Alarm 10 minutes
Alarm minutes
0059
Alarm minutes
1FFF2
ALM0
Alarm 10 seconds
Alarm seconds
0059
Alarm seconds
1FFF1
0.1 seconds
0.01 seconds
0099
0.1/0.01 seconds
1FFF0
WDF
AF
PWRF
BLF
PF
X
X
X
Flags
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
BLF = 1 for low battery.
OSC = 1 stops the clock oscillator.
Interrupt enables are cleared on power-up.
Table 1. bq4842 Clock and Control Register Map
bq4842Y
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock on or
off. If the bq4842Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
Calibrating the Clock
The bq4842Y real-time clock is driven by a quartz con-
trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4842Y
package along with the battery. The clock accuracy of
the bq4842Y module is tested to be within 20ppm or
about 1 minute per month at 25C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4842Y of-
fers onboard software clock calibration.
The user can
adjust the calibration based on the typical operating
temperature of individual applications.
The software calibration bits are located in the control reg-
ister. Bits D0D4 control the magnitude of correction, and
bit D5 the direction (positive or negative) of correction.
Assuming that the oscillator is running at exactly 32,786
Hz, each calibration step of D0D4 adjusts the clock rate
by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm
(-5.35 seconds per month) depending on the value of the
sign bit D5. When the sign bit is 1, positive adjustment
occurs; a 0 activates negative adjustment. The total range
of clock calibration is +5.5 or -2.75 minutes per month.
Two methods can be used to ascertain how much cali-
bration a given bq4842Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system's environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.
The second approach uses a bq4842Y test mode. When the
frequency test mode enable bit FTE in the days register is
set to a 1, and the oscillator is running at exactly 32,768 Hz,
the LSB of the seconds register toggles at 512 Hz. Any de-
viation from 512 Hz indicates the degree and direction of os-
cillator frequency shift at the test temperature. For example,
a reading of 512.01024 Hz indicates a (1E6*0.01024)/512 or
+20 ppm oscillator frequency error, requiring ten steps of
negative calibration (10*-2.034 or -20.34) or 001010 to be
loaded into the calibration byte for correction. To read the
test frequency, the bq4842Y must be selected and held in an
extended read of the seconds register, location 1FFF9, with-
5
Sept. 1996 C
Bits
Description
ABE
Alarm interrupt enable in
battery-backup mode
AF
Alarm interrupt flag
AIE
Alarm interrupt enable
ALM0ALM3
Alarm repeat rate
BLF
Battery-low flag
BM0BM4
Watchdog multiplier
FTE
Frequency test mode enable
OSC
Oscillator stop
PF
Periodic interrupt flag
PIE
Periodic interrupt enable
PWRF
Power-fail interrupt flag
PWRIE
Power-fail interrupt enable
R
Read clock enable
RS0RS3
Periodic interrupt rate
S
Calibration sign
W
Write clock enable
WD0WD1
Watchdog resolution
WDF
Watchdog flag
WDS
Watchdog steering
Table 2. Clock and Control Register Bits
Figure 3. Frequency Error
bq4842Y
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