Features
Real-Time Clock counts seconds
through years in BCD format
On-chip battery-backup switchover
circuit with nonvolatile control for
external SRAM
Less than 500nA of clock opera-
tion current in backup mode
Microprocessor reset valid to
V
CC
= V
SS
Independent watchdog timer
with a programmable time-out
period
Power-fail interrupt warning
Programmable clock alarm inter-
rupt active in battery-backup
mode
Programmable periodic interrupt
Battery-low warning
General Description
The bq4845 Real-Time Clock is a
low-power microprocessor periph-
eral that integrates a time-of-day
clock, a 100-year calendar, and a
CPU supervisor in a 28-pin SOIC or
DIP. The bq4845 is ideal for fax ma-
chines, copiers, industrial control
systems, point-of-sale terminals,
data loggers, and computers.
The bq4845 provides direct connec-
tions for a 32.768KHz quartz crystal
and a 3V backup battery. Through
the use of the conditional chip en-
able output (CE
OUT
) and battery
voltage output (V
OUT
) pins, the
bq4845 can write-protect and make
nonvolatile external SRAMs. The
backup cell powers the real-time
clock and maintains SRAM infor-
mation in the absence of system
voltage.
The bq4845 contains a temperature-
compensated reference and comparator
circuit that monitors the status of its
voltage supply. When the bq4845 de-
tects an out-of-tolerance condition, it
generates an interrupt warning and
subsequently a microprocessor reset.
The reset stays active for 200ms after
V
CC
rises within tolerance, to allow for
power supply and processor stabiliza-
tion.
The bq4845 also has a built-in
watchdog timer to monitor processor
operation. If the microprocessor does
not toggle the watchdog input (WDI)
within the programmed time-out pe-
riod, the bq4845 asserts WDO and
RST. WDI unconnected disables the
watchdog timer.
The bq4845 can generate other in-
terrupts based on a clock alarm con-
dition or a periodic setting. The
alarm interrupt can be set to occur
from once per second to once per
month. The alarm can be made active
in the battery-backup mode to serve
as a system wake-up call. For inter-
rupts at a rate beyond once per sec-
ond, the periodic interrupt can be pro-
grammed with periods of 30.5
s to
500ms.
1
Aug. 1995
1
PN484501.eps
28-DIP or SOIC
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
9
10
20
19
11
12
18
17
13
14
V
CC
WE
CE
IN
CE
OUT
BC
WDI
OE
CS
V
SS
DQ
7
DQ
8
DQ
5
DQ
4
DQ
3
16
15
V
OUT
X
1
X
2
WDO
INT
RST
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
Pin Connections
A
0
A
3
Clock/control address
inputs
DQ
0
DQ
7
Data inputs/outputs
WE
Write enable
OE
Output enable
CS
Chip select input
CE
IN
External RAM chip
enable
CE
OUT
Conditional RAM chip
enable
X1X2
Crystal inputs
Pin Names
BC
Backup battery input
V
OUT
Back-up battery output
INT
Interrupt output
RST
Microprocessor reset
WDI
Watchdog input
WDO
Watchdog output
V
CC
+5V supply
V
SS
Ground
bq4845/bq4845Y
Parallel RTC With CPU Supervisor
Functional Description
Figure 1 is a block diagram of the bq4845. The follow-
ing sections describe the bq4845 functional operation
including clock interface, data-retention modes,
power-on reset timing, watchdog timer activation, and
interrupt generation.
2
Figure 1. Block Diagram
V
CC
CS
OE
WE
CE
OUT
V
OUT
Mode
DQ
Power
< V
CC
(max.)
V
IH
X
X
CE
IN
V
OUT1
Deselect
High Z
Standby
V
IL
X
V
IL
CE
IN
V
OUT1
Write
D
IN
Active
> V
CC
(min.)
V
IL
V
IL
V
IH
CE
IN
V
OUT1
Read
D
OUT
Active
V
IL
V
IH
V
IH
CE
IN
V
OUT1
Read
High Z
Active
< V
PFD
(min.) > V
SO
X
X
X
V
OH
V
OUT1
Deselect
High Z
CMOS standby
V
SO
X
X
X
V
OHB
V
OUT2
Deselect
High Z
Battery-backup mode
Truth Table
Aug. 1995
bq4845/bq4845Y
Pin Descriptions
X1X2
Crystal inputs
X1X2
are
a
direct
connection
for
a
32.768kHZ, 6pF crystal.
RST
Reset output
RST goes low whenever V
CC
falls below the
power fail threshold. RST will remain low for
200ms typical after V
CC
crosses the threshold
on power-up. RST also goes low whenever a
watchdog timeout occurs.
RST is an open-
drain output.
INT
Interrupt output
INT goes low when a power fail, periodic, or
alarm condition occurs. INT is an open-drain
output.
WDI
Watchdog input
WDI is a three-level input. If WDI remains
either high or low for longer than the
watchdog time-out period (1.5 seconds de-
fault), WDO goes low. WDO remains low
until the next transition at WDI. Leaving
WDI unconnected disables the watchdog
function. WDI connects to an internal volt-
age divider between V
OUT
and V
SS
, which
sets it to mid-supply when left uncon-
nected.
WDO
Watchdog output
WDO goes low if WDI remains either high
or low longer than the watchdog time-out
period. WDO returns high on the next tran-
sition at WDI. WDO remains high if WDI is
unconnected.
A
0
A
3
Clock address inputs
A
0
A
3
allow access to the 16 bytes of real-
time clock and control registers.
DQ
0
DQ
7
Data input and output
DQ
0
DQ
7
provide x8 data for real-time clock
information. These pins connect to the mem-
ory data bus.
V
SS
Ground
CS
Chip select
OE
Output enable
OE provides the read control for the RTC
memory locations.
CE
OUT
Chip enable output
CE
OUT
goes low only when CE
IN
is low and
V
CC
is above the power fail threshold. If
CE
IN
is low, and power fail occurs, CE
OUT
stays low for 100
s or until CE
IN
goes high,
whichever occurs first.
CE
IN
Chip enable input
CE
IN
is the input to the chip-enable gating
circuit.
BC
Backup battery input
BC should be connected to a 3V backup
cell. A voltage within the V
BC
range on the
BC pin should be present upon power up to
provide proper oscillator start-up.
V
OUT
Output supply voltage
V
OUT
provides the higher of V
CC
or V
BC
,
switched internally, to supply external
RAM.
WE
Write enable
WE provides the write control for the RTC
memory locations.
V
CC
Input supply voltage
+5V input
3
Aug. 1995
bq4845/bq4845Y
Address Map
The bq4845 provides 16 bytes of clock and control status
registers. Table 1 is a map of the bq4845 registers, and
Table 2 describes the register bits.
Clock Memory Interface
The bq4845 has the same interface for clock/calendar
and control information as standard SRAM. To read and
write to these locations, the user must put the bq4845 in
the proper mode and meet the timing requirements.
Read Mode
The bq4845 is in read mode whenever OE (Output en-
able) is low and CS (chip select) is low. The unique ad-
dress, specified by the 4 address inputs, defines which
one of the 16 clock/calendar bytes is to be accessed. The
bq4845 makes valid data available at the data I/O pins
within t
AA
(address access time). This occurs after the
last address input signal is stable, and providing the CS
and OE (output enable) access times are met. If the CS
and OE access times are not met, valid data is available
after the latter of chip select access time (t
ACS
) or output
enable access time (t
OE
).
CS and OE control the state of the eight three-state
data I/O signals. If the outputs are activated before t
AA
,
4
Ad-
dress
(h)
D7
D6
D5
D4
D3
D2
D1
D0
12-Hour
Range (h)
Register
0
0
10-second digit
1-second digit
0059
Seconds
1
ALM1
ALM0
1-second digit
0059
Seconds alarm
10-second digit
2
0
10-minute digit
1-minute digit
0059
Minutes
3
ALM1
ALM0
1-minute digit
0059
Minutes alarm
10-minute digit
4
PM/AM
0
10-hour digit
1-hour digit
0112 AM/ 81 92 PM Hours
5
ALM1
ALM0
10-hour digit
1-hour digit
0112 AM/ 8192 PM Hours alarm
PM/AM
6
0
0
10-day digit
1-day digit
0131
Day
7
ALM1
ALM0
10-day digit
1-day digit
0131
Day alarm
8
0
0
0
Day-of-week digit
0107
Day-of-week
9
0
0
0
10 mo.
1-month digit
0112
Month
A
10-year digit
1-year digit
0099
Year
B
*
WD2
WD1
WD0
RS3
RS2
RS1
RS0
Programmable
rates
C
*
*
AIE
PIE
PWRIE ABE
Interrupt en-
ables
D
*
*
AF
PF
PWRF BVF
Flags
E
*
*
UTI
STOP
24/12
DSE
Control
F
*
*
*
*
*
*
*
*
Unused
Notes:
* = Unused bits; unwritable and read as 0.
0 = should be set to 0 for valid time/calendar range.
Clock calendar data in BCD. Automatic leap year adjustment.
PM/AM = 1 for PM; PM/AM = 0 for AM.
DSE = 1 enables daylight savings adjustment.
24/12 = 1 enables 24-hour data representation; 24/12 = 0 enables 12-hour data representation.
Day-of-Week coded as Sunday = 1 through Saturday = 7.
BVF = 1 for valid battery.
STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode.
Table 1. bq4845 Clock and Control Register Map
Aug. 1995
bq4845/bq4845Y
the data lines are driven to an indeterminate state until
t
AA
. If the address inputs are changed while CS and OE
remain low, output data remains valid for t
OH
(output
data hold time), but goes indeterminate until the next
address access.
Write Mode
The bq4845 is in write mode whenever WE and CS are
active.
The start of a write is referenced from the
latter-occurring falling edge of WE or CS. A write is ter-
minated by the earlier rising edge of WE or CS. The ad-
dresses must be held valid throughout the cycle. CS or
WE must return high for a minimum of t
WR2
from CS or
t
WR1
from WE prior to the initiation of another read or
write cycle.
Data-in must be valid t
DW
prior to the end of write and
remain valid for t
DH1
or t
DH2
afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CS and OE, a low on WE disables the outputs t
WZ
after
WE falls.
Reading the Clock
Once every second, the user-accessible clock/calendar lo-
cations are updated simultaneously from the internal
real time counters. To prevent reading data in transi-
tion, updates to the bq4845 clock registers should be
halted. Updating is halted by setting the update trans-
fer inhibit (UTI) bit D3 of the control register E. As long
as the UTI bit is 1, updates to user-accessible clock loca-
tions are inhibited. Once the frozen clock information is
retrieved by reading the appropriate clock memory loca-
tions, the UTI bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because
the internal counters are not halted by setting the UTI
bit, reading the clock locations has no effect on clock ac-
curacy. Once the UTI bit is reset to 0, the internal regis-
ters update within one second the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
Setting the Clock
The UTI bit must also be used to set the bq4845 clock.
Once set, the locations can be written with the desired
information in BCD format. Resetting the UTI bit to 0
causes the written values to be transferred to the inter-
nal clock counters and allows updates to the user-
accessible registers to resume within one second.
Stopping and Starting the Clock Oscillator
The bq4845 clock can be programmed to turn off when
the part goes into battery back-up mode by setting
STOP to 0 prior to power down. If the board using the
bq4845 is to spend a significant period of time in stor-
age, the STOP bit can be used to preserve some battery
capacity. STOP set to 1 keeps the clock running when
V
CC
drops below V
SO
. With V
CC
greater than V
SO
, the
bq4845 clock runs regardless of the state of STOP.
Power-Down/Power-Up Cycle
The bq4845 continuously monitors V
CC
for out-of-
tolerance. During a power failure, when V
CC
falls below
V
PFD
, the bq4845 write-protects the clock and storage
registers.
When V
CC
is below V
BC
(3V typical), the
power source is switched to BC.
RTC operation and
storage data are sustained by a valid backup energy
source.
When V
CC
is above V
BC
, the power source is
V
CC
. Write-protection continues for t
CSR
time after V
CC
rises above V
PFD
.
An external CMOS static RAM is battery-backed using
the V
OUT
and chip enable output pins from the bq4845.
As the voltage input V
CC
slews down during a power
failure, the chip enable output, CE
OUT,
is forced inactive
independent of the chip enable input CE
IN.
5
Bits
Description
24/12
24- or 12-hour representation
ABE
Alarm interrupt enable in
battery-backup mode
AF
Alarm interrupt flag
AIE
Alarm interrupt enable
ALM0ALM1
Alarm mask bits
BVF
Battery-valid flag
DSE
Daylight savings time enable
PF
Periodic interrupt flag
PIE
Periodic interrupt enable
PM/AM
PM or AM indication
PWRF
Power-fail interrupt flag
PWRIE
Power-fail interrupt enable
RS0RS3
Periodic interrupt rate
STOP
Oscillator stop and start
UTI
Update transfer inhibit
WD0 - WD2
Watchdog time-out rate
Table 2. Clock and Control Register Bits
Aug. 1995
bq4845/bq4845Y
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