Features
Integrated SRAM, real-time
clock, crystal, power-fail control
circuit, and battery
Real-Time Clock counts seconds
through years in BCD format
RAM-like clock access
Pin-compatible with industry-
standard 512K x 8 SRAMs
Unlimited write cycles
10-year minimum data retention
and clock operation in the absence
of power
Automatic power-fail chip dese-
lect and write-protection
Software clock calibration for
g r e a t e r t h a n
1 m i n u t e p e r
month accuracy
General Description
The bq4850Y RTC Module is a non-
volatile 4,194,304-bit SRAM organ-
ized as 524,288 words by 8 bits with
an integral accessible real-time
clock.
The device combines an internal lith-
ium battery, quartz crystal, clock and
power-fail chip, and a full CMOS
SRAM in a plastic 32-pin DIP mod-
ule. The RTC Module directly re-
places industry-standard SRAMs and
also fits into many EPROM and EE-
PROM sockets without any require-
ment for special write timing or limi-
tations on the number of write cycles.
Registers for the real-time clock,
alarm and other special
functions
are located in registers 7FFF8h
7FFFFh of the memory array.
The clock and alarm registers are
dual-port read/write SRAM loca-
tions that are updated once per sec-
ond by a clock control circuit from
the internal clock counters.
The
dual-port registers allow clock up-
dates to occur without interrupting
normal access to the rest of the
SRAM array.
The bq4850Y also contains a power-
fail-detect circuit. The circuit dese-
lects the device whenever V
CC
falls
below tolerance, providing a high de-
gree of data security. The battery is
electrically isolated when shipped
from the factory to provide maxi-
mum battery capacity. The battery
remains disconnected until the first
application of V
CC
.
1
bq4850Y
RTC Module With 512Kx8 NVSRAM
1
PN485001.eps
32-Pin DIP Module
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
9
10
24
23
11
12
22
21
13
14
20
19
15
16
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Pin Names
A
0
A
18
Address input
CE
Chip enable
WE
Write enable
OE
Output enable
DQ
0
DQ
7
Data in/data out
V
CC
+5 volts
V
SS
Ground
Aug. 1996
Pin Connections
Functional Description
Figure 1 is a block diagram of the bq4850Y. The follow-
ing sections describe the bq4850Y functional operation,
including memory and clock interface, and data-
retention modes.
2
BD-961
16 1 MUX
4
64
.
.
-
-
.
.
64
8
.
.
-
CE
OE
WE
AD -AD
0
18
CC
V
Bus
I/F
P
Time-
Base
Oscillator
Control/Status
Registers
Clock Alarm and
Calendar Bytes
Clock/Calendar
Update
Power-
Fail
Control
3
:
7
0
DQ -DQ
Storage
Registers
(524,288 Bytes)
User Buffer
(8 Bytes)
Quartz
Internal
Crystal
Internal
Battery
Write-
Protect
Figure 1. Block Diagram
V
CC
CE
OE
WE
Mode
DQ
Power
< V
CC
(max.)
V
IH
X
X
Deselect
High Z
Standby
V
IL
X
V
IL
Write
D
IN
Active
> V
CC
(min.)
V
IL
V
IL
V
IH
Read
D
OUT
Active
V
IL
V
IH
V
IH
Read
High Z
Active
< V
PFD
(min.) > V
SO
X
X
X
Deselect
High Z
CMOS standby
V
SO
X
X
X
Deselect
High Z
Battery-backup mode
Truth Table
Aug. 1996
bq4850Y
Address Map
The bq4850Y provides 8 bytes of clock and control status
registers and 524,288 bytes of storage RAM.
Figure 2 illustrates the address map for the bq4850Y.
Table 1 is a map of the bq4850Y registers.
3
Address
D7
D6
D5
D4
D3
D2
D1
D0
Range (h)
Register
7FFFF
10 Years
Year
0099
Year
7FFFE
X
X
X
10 Month
Month
0112
Month
7FFFD
X
X
10 Date
Date
0131
Date
7FFFC
X
FTE
X
X
X
Day
0107
Days
7FFFB
X
X
10 Hours
Hours
0023
Hours
7FFFA
X
10 Minutes
Minutes
0059
Minutes
7FFF9
OSC
10 Seconds
Seconds
0059
Seconds
7FFF8
W
R
S
Calibration
0031
Control
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
OSC = 1 stops the clock oscillator.
Table 1. bq4850Y Clock and Control Register Map
Registers
Control Status
Clock and
8 Bytes
RAM
Storage
Bytes
32,760
7FFFF
7FFF7
7FFF8
0000
7
6
5
4
3
2
1
0
7FFF8
7FFF9
7FFFA
7FFFC
7FFFD
7FFFE
7FFFF
Control
Seconds
Minutes
Hours
Days
Date
Month
Year
MM-961
7FFFB
Figure 2. Address Map
Aug. 1996
bq4850Y
Memory Interface
Read Mode
The bq4850Y is in read mode whenever OE (output en-
able) is low and CE (chip enable) is low. The device ar-
chitecture allows ripple-through access of data from
eight of 4,194,304 locations in the static storage array.
Thus, the unique address specified by the 19 address in-
puts defines which one of the 524,288 bytes of data is to
be accessed. Valid data is available at the data I/O pins
within t
AA
(address access time) after the last address
input signal is stable, providing that the CE and OE
(output enable) access times are also satisfied. If the CE
and OE access times are not met, valid data is available
after the latter of chip enable access time (t
ACE
) or out-
put enable access time (t
OE
).
CE and OE control the state of the eight three-state
data I/O signals. If the outputs are activated before t
AA
,
the data lines are driven to an indeterminate state until
t
AA
. If the address inputs are changed while CE and OE
remain low, output data remains valid for t
OH
(output
data hold time), but goes indeterminate until the next
address access.
Write Mode
The bq4850Y is in write mode whenever WE and CE are
active.
The start of a write is referenced from the
latter-occurring falling edge of WE or CE. A write is ter-
minated by the earlier rising edge of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return high for a minimum of t
WR2
from CE or
t
WR1
from WE prior to the initiation of another read or
write cycle.
Data-in must be valid t
DW
prior to the end of write and
remain valid for t
DH1
or t
DH2
afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CE and OE, a low on WE disables the outputs t
WZ
after
WE falls.
Data-Retention Mode
With valid V
CC
applied, the bq4850Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself t
WPT
after V
CC
falls below V
PFD
.
All outputs become high impedance, and all inputs are
treated as "don't care."
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory
cycle fails to terminate within time t
W P T
, write-
protection takes place. When V
CC
drops below V
SO
, the
control circuit switches power to the internal energy
source, which preserves data.
The internal coin cell maintains data in the bq4850Y af-
ter the initial application of V
CC
for an accumulated pe-
riod of at least 10 years when V
CC
is less than V
SO
. As
system power returns and Vcc rises above V
SO
, the bat-
tery is disconnected, and the power supply is switched to
external V
CC
. Write-protection continues for t
CER
after
V
CC
reaches V
PFD
to allow for processor stabilization.
After t
CER
, normal RAM operation can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4850Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4850Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because the
internal counters are not halted by setting the read bit,
reading the clock locations has no effect on clock accu-
racy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
Setting the Clock
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (7FFFF7FFF9).
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock on or
off. If the bq4850Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
4
Aug. 1996
bq4850Y
Calibrating the Clock
The bq4850Y real-time clock is driven by a quartz con-
trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4850Y
package along with the battery. The clock accuracy of
the bq4850Y module is tested to be within 20ppm or
about 1 minute per month at 25C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4850Y of-
fers onboard software clock calibration.
The user can
adjust the calibration based on the typical operating
temperature of individual applications.
The software calibration bits are located in the control
register. Bits D0D4 control the magnitude of correc-
tion, and bit D5 the direction (positive or negative) of
correction. Assuming that the oscillator is running at
exactly 32,786 Hz, each calibration step of D0D4 ad-
justs the clock rate by +4.068 ppm (+10.7 seconds per
month) or -2.034 ppm (-5.35 seconds per month) depend-
ing on the value of the sign bit D5. When the sign bit is
1, positive adjustment occurs; a 0 activates negative ad-
justment. The total range of clock calibration is +5.5 or
-2.75 minutes per month.
Two methods can be used to ascertain how much cali-
bration a given bq4850Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system's environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.
The second approach uses a bq4850Y test mode. When
the frequency test mode enable bit FTE in the days reg-
ister is set to a 1, and the oscillator is running at exactly
32,768 Hz, the LSB of the seconds register toggles at
512 Hz. Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz
indicates a (1E6
0.01024)/512 or +20 ppm oscillator fre-
quency error, requiring ten steps of negative calibration
(10
-2.034 or -20.34) or 001010 to be loaded into the cali-
bration byte for correction. To read the test frequency,
the bq4850Y must be selected and held in an extended
read of the seconds register, location 7FFF9, without
having the read bit set. The frequency appears on DQ0.
The FTE bit must be set using the write bit control. The
FTE bit must be reset to 0 for normal clock operation to
resume.
5
bq4850Y
Aug. 1996
-120
-100
-80
-60
-40
-20
0
-30 -20 -10 0 10 20 30 40 50 60 70
Temperature ( C)
Frequency Error
GR485001
Figure 3. Frequency Error
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