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Электронный компонент: CD4049UBF

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1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright
2004, Texas Instruments Incorporated
Data sheet acquired from Harris Semiconductor
SCHS046I
CD4049UB, CD4050B
CMOS Hex Buffer/Converters
The CD4049UB and CD4050B devices are inverting and
non-inverting hex buffers, respectively, and feature logic-
level conversion using only one supply voltage (V
CC
). The
input-signal high level (V
IH
) can exceed the V
CC
supply
voltage when these devices are used for logic-level
conversions. These devices are intended for use as CMOS
to DTL/TTL converters and can drive directly two DTL/TTL
loads. (V
CC
= 5V, V
OL
0.4V, and I
OL
3.3mA.)
The CD4049UB and CD4050B are designated as
replacements for CD4009UB and CD4010B, respectively.
Because the CD4049UB and CD4050B require only one
power supply, they are preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB
and CD4010B in all inverter, current driver, or logic-level
conversion applications. In these applications the
CD4049UB and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and can be
substituted for these devices in existing as well as in new
designs. Terminal No. 16 is not connected internally on the
CD4049UB or CD4050B, therefore, connection to this
terminal is of no consequence to circuit operation. For
applications not requiring high sink-current or voltage
conversion, the CD4069UB Hex Inverter is recommended.
Features
CD4049UB Inverting
CD4050B Non-Inverting
High Sink Current for Driving 2 TTL Loads
High-To-Low Level Logic Conversion
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
A at 18V Over Full Package
Temperature Range; 100nA at 18V and 25
o
C
5V, 10V and 15V Parametric Ratings
Applications
CMOS to DTL/TTL Hex Converter
CMOS Current "Sink" or "Source" Driver
CMOS High-To-Low Logic Level Converter
Pinouts
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
CD4049UBF3A
-55 to 125
16 Ld CERDIP
CD4050BF3A
-55 to 125
16 Ld CERDIP
CD4049UBD
-55 to 125
16 Ld SOIC
CD4049UBDR
-55 to 125
16 Ld SOIC
CD4049UBDT
-55 to 125
16 Ld SOIC
CD4049UBDW
-55 to 125
16 Ld SOIC
CD4049UBDWR
-55 to 125
16 Ld SOIC
CD4049UBE
-55 to 125
16 Ld PDIP
CD4049UBNSR
-55 to 125
16 Ld SOP
CD4049UBPW
-55 to 125
16 Ld TSSOP
CD4049UBPWR
-55 to 125
16 Ld TSSOP
CD4050BD
-55 to 125
16 Ld SOIC
CD4050BDR
-55 to 125
16 Ld SOIC
CD4050UBDT
-55 to 125
16 Ld SOIC
CD4050BDW
-55 to 125
16 Ld SOIC
CD4050BDWR
-55 to 125
16 Ld SOIC
CD4050BE
-55 to 125
16 Ld PDIP
CD4050NSR
-55 to 125
16 Ld SOP
CD4050BPW
-55 to 125
16 Ld TSSOP
CD4050BPWR
-55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffix R denotes tape
and reel. The suffix T denotes a small-quantity reel of 250.
CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)
TOP VIEW
CD4050B (PDIP, CERDIP, SOIC, SOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V
CC
G = A
A
H = B
B
I = C
V
SS
C
NC
F
NC
K = E
E
J = D
D
L = F
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V
CC
G = A
A
H = B
B
I = C
V
SS
C
NC
F
NC
K = E
E
J = D
D
L = F
August 1998 - Revised May 2004
[ /Title
(CD40
49UB,
CD405
0B)
/Sub-
ject
(CMO
S Hex
Buffer/
Con-
verters)
/Autho
r ()
/Key-
words
(Harris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
2
Functional Block Diagrams
CD4049UB
CD4050B
3
2
A
G = A
5
4
B
H = B
7
6
C
I = C
9
10
D
J = D
11
12
E
K = E
14
15
F
L = F
1
8
V
CC
V
SS
NC = 13
NC = 16
3
2
A
G = A
5
4
B
H = B
7
6
C
I = C
9
10
D
J = D
11
12
E
K = E
14
15
F
L = F
1
8
V
CC
V
SS
NC = 13
NC = 16
Schematic Diagrams
FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6
IDENTICAL UNITS
FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6
IDENTICAL UNITS
V
CC
OUT
V
SS
P
N
R
IN
P
N
R
IN
V
CC
OUT
V
SS
P
N
CD4049UB, CD4050B
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Package Thermal Impedance,
JA
(see Note1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . . 65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265
o
C
SOIC - Lead Tips Only
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
TEST CONDITIONS
LIMITS AT INDICATED TEMPERATURE (
o
C)
UNITS
-55
-40
85
125
25
V
O
(V)
V
IN
(V)
V
CC
(V)
MIN
TYP
MAX
Quiescent Device Current
I
DD
(Max)
-
0,5
5
1
1
30
30
-
0.02
1
A
-
0,10
10
2
2
60
60
-
0.02
2
A
-
0,15
15
4
4
120
120
-
0.02
4
A
-
0,20
20
20
20
600
600
-
0.04
20
A
Output Low (Sink) Current
I
OL
(Min)
0.4
0,5
4.5
3.3
3.1
2.1
1.8
2.6
5.2
-
mA
0.4
0,5
5
4
3.8
2.9
2.4
3.2
6.4
-
mA
0.5
0,10
10
10
9.6
6.6
5.6
8
16
-
mA
1.5
0,15
15
26
25
20
18
24
48
-
mA
Output High (Source) Current
I
OH
(Min)
4.6
0,5
5
-0.81
-0.73
-0.58
-0.48
-0.65
-1.2
-
mA
2.5
0,5
5
-2.6
-2.4
-1.9
-1.55
-2.1
-3.9
-
mA
9.5
0,10
10
-2.0
-1.8
-1.35
-1.18
-1.65
-3.0
-
mA
13.5
0,15
15
-5.2
-4.8
-3.5
-3.1
-4.3
-8.0
-
mA
Out Voltage Low Level
V
OL
(Max)
-
0,5
5
0.05
0.05
0.05
0.05
-
0
0.05
V
-
0,10
10
0.05
0.05
0.05
0.05
-
0
0.05
V
-
0,15
15
0.05
0.05
0.05
0.05
-
0
0.05
V
Output Voltage High Level
V
OH
(Min)
-
0,5
5
4.95
4.95
4.95
4.95
4.95
5
-
V
-
0,10
10
9.95
9.95
9.95
9.95
9.95
10
-
V
-
0,15
15
14.95
14.95
14.95
14.95
14.95
15
-
V
Input Low Voltage, V
IL
(Max)
CD4049UB
4.5
-
5
1
1
1
1
-
-
1
V
9
-
10
2
2
2
2
-
-
2
V
13.5
-
15
2.5
2.5
2.5
2.5
-
-
2.5
V
Input Low Voltage, V
IL
(Max)
CD4050B
0.5
-
5
1.5
1.5
1.5
1.5
-
-
1.5
V
1
-
10
3
3
3
3
-
-
3
V
1.5
-
15
4
4
4
4
-
-
4
V
CD4049UB, CD4050B
4
Input High Voltage, V
IH
Min
CD4049UB
0.5
-
5
4
4
4
4
4
-
-
V
1
-
10
8
8
8
8
8
-
-
V
1.5
-
15
12.5
12.5
12.5
12.5
12.5
-
-
V
Input High Voltage, V
IH
Min
CD4050B
4.5
-
5
3.5
3.5
3.5
3.5
3.5
-
-
V
9
-
10
7
7
7
7
7
-
-
V
13.5
-
15
11
11
11
11
11
-
-
V
Input Current, I
IN
Max
-
0,18
18
0.1
0.1
1
1
-
10
-5
0.1
A
DC Electrical Specifications
(Continued)
PARAMETER
TEST CONDITIONS
LIMITS AT INDICATED TEMPERATURE (
o
C)
UNITS
-55
-40
85
125
25
V
O
(V)
V
IN
(V)
V
CC
(V)
MIN
TYP
MAX
AC Electrical Specifications
T
A
= 25
o
C, Input t
r
, t
f
= 20ns, C
L
= 50pF, R
L
= 200k
PARAMETER
TEST CONDITIONS
LIMITS (ALL PACKAGES)
UNITS
V
IN
V
CC
TYP
MAX
Propagation Delay Time
Low to High, t
PLH
CD4049UB
5
5
60
120
ns
10
10
32
65
ns
10
5
45
90
ns
15
15
25
50
ns
15
5
45
90
ns
Propagation Delay Time
Low to High, t
PLH
CD4050B
5
5
70
140
ns
10
10
40
80
ns
10
5
45
90
ns
15
15
30
60
ns
15
5
40
80
ns
Propagation Delay Time
High to Low, t
PHL
CD4049UB
5
5
32
65
ns
10
10
20
40
ns
10
5
15
30
ns
15
15
15
30
ns
15
5
10
20
ns
Propagation Delay Time
High to Low, t
PHL
CD4050B
5
5
55
110
ns
10
10
22
55
ns
10
5
50
100
ns
15
15
15
30
ns
15
5
50
100
ns
Transition Time, Low to High, t
TLH
5
5
80
160
ns
10
10
40
80
ns
15
15
30
60
ns
Transition Time, High to Low, t
THL
5
5
30
60
ns
10
10
20
40
ns
15
15
15
30
ns
CD4049UB, CD4050B
5
Input Capacitance, C
IN
CD4049UB
-
-
15
22.5
pF
Input Capacitance, C
IN
CD4050B
-
-
5
7.5
pF
AC Electrical Specifications
T
A
= 25
o
C, Input t
r
, t
f
= 20ns, C
L
= 50pF, R
L
= 200k
(Continued)
PARAMETER
TEST CONDITIONS
LIMITS (ALL PACKAGES)
UNITS
V
IN
V
CC
TYP
MAX
Typical Performance Curves
FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS FOR CD4049UB
FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS FOR CD4050B
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN
CHARACTERISTICS
5
4
3
2
1
0
1
2
3
4
V
I
, INPUT VOLTAGE (V)
V
O
, OUTPUT V
O
L
T
A
GE (V)
T
A
= 25
o
C
SUPPLY VOLTAGE (V
CC
) = 5V
MAXIMUM
MINIMUM
5
4
3
2
1
0
1
2
3
4
V
I
, INPUT VOLTAGE (V)
V
O
, OUTPUT V
O
L
T
A
GE (V)
T
A
= 25
o
C
SUPPLY VOLTAGE (V
CC
) = 5V
MAXIMUM
MINIMUM
50
40
30
20
10
0
1
2
3
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
OL
, OUTPUT LO
W (SINK) CURRENT (mA)
T
A
= 25
o
C
GATE TO SOURCE VOLTAGE (V
GS
) = 5V
10V
15V
60
70
5
6
7
8
50
40
30
20
10
0
1
2
3
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
OL
, OUTPUT LO
W (SINK) CURRENT (mA)
T
A
= 25
o
C
GATE TO SOURCE VOLTAGE (V
GS
) = 5V
10V
15V
60
70
5
6
7
8
CD4049UB, CD4050B