CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Internal Look-Ahead for Fast Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2 kV ESD Protection per
MIL-STD-883, Method 3015
D
Package Options Include Plastic
Small-Outline (M), Standard Plastic (E) and
Ceramic (F) DIPs
description
The CD54AC161 and CD74AC161 devices are 4-bit binary counters. These synchronous, presettable counters
feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation
eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters.
A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,
regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
A
high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The CD54AC161 is characterized for operation over the full military temperature range of 55
C to 125
C.
The CD74AC161 is characterized for operation from 40
C to 85
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
CD54AC161 . . . F PACKAGE
CD74AC161 . . . E OR M PACKAGE
(TOP VIEW)
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
CLK
ENP
ENT
LOAD
A,B,C,D
Qn
RCO
FUNCTION
L
X
X
X
X
X
L
L
Reset (clear)
H
X
X
l
l
L
L
Parallel load
H
X
X
l
h
H
Note 1
Parallel load
H
h
h
h
X
Count
Note 1
Count
H
X
l
X
h
X
qn
Note 1
Inhibit
H
X
X
l
h
X
qn
L
Inhibit
H = high level, L = low level, X = don't care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition,
= CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count (HHHH).
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
14
13
12
11
CTRDIV16
LOAD
1,5D
3
A
4
B
5
C
6
D
CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT
RCO
15
3CT=15
QA
QB
QC
QD
G4
7
ENP
2
CLK
CLR
[1]
[2]
[4]
[8]
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
QB
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
QC
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
QD
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD
CK
CK
R
LD
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1
LD (Load)
Q (Output)
G2
TE (Toggle Enable)
CK (Clock)
G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD
LD
D
R
CK
CK
CK
CK
Q
The origins of LD and CK are shown in the logic diagram of the overall device.
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1.
Clear outputs to zero (asynchronous)
2.
Preset to binary 12
3.
Count to 13, 14, 15, 0, 1, and 2
4.
Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Preset
Count
Inhibit
12
13
14
15
0
1
2
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 V or V
I
> V
CC
) (see Note 2)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 V or V
O
> V
CC
) (see Note 2)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
> 0 V or V
O
< V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): E package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
TA = 25
C
CD54AC161
CD74AC161
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
1.5
5.5
1.5
5.5
1.5
5.5
V
VCC = 1.5 V
1.2
1.2
1.2
VIH
High-level input voltage
VCC = 3 V
2.1
2.1
2.1
V
VCC = 5.5 V
3.85
3.85
3.85
VCC = 1.5 V
0.3
0.3
0.3
VIL
Low-level input voltage
VCC = 3 V
0.9
0.9
0.9
V
VCC = 5.5 V
1.65
1.65
1.65
VI
Input voltage
0
VCC
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
0
VCC
V
IOH
High-level output current
24
24
24
mA
IOL
Low-level output current
24
24
24
mA
t/
v
Input transition rise or fall rate
VCC = 1.5 V to 3 V
0
50
0
50
0
50
ns
t/
v
Input transition rise or fall rate
VCC = 3.6 V to 5.5 V
0
20
0
20
0
20
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
CD54AC161
CD74AC161
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1.5 V
1.4
1.4
1.4
IOH = 50
A
3 V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
VOH
VI = VIH or VIL
IOH = 4 mA
3 V
2.58
2.4
2.48
V
IOH = 24 mA
4.5 V
3.94
3.7
3.8
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
1.5 V
0.1
0.1
0.1
IOL = 50
A
3 V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
VOL
VI = VIH or VIL
IOL = 12 mA
3 V
0.36
0.5
0.44
V
IOL = 24 mA
4.5 V
0.36
0.5
0.44
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
160
80
A
Ci
10
10
10
pF
Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-
transmission-line drive capability at 85
C and 75-
transmission-line drive capability at 125
C.
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
CD54AC161
CD74AC161
UNIT
VCC
MIN
MAX
MIN
MAX
UNIT
1.5 V
7
8
fclock
Clock frequency
3.3 V
0.3 V
64
73
MHz
5 V
0.5 V
90
103
1.5 V
69
61
CLK high or low
3.3 V
0.3 V
7.7
6.8
t
Pulse duration
5 V
0.5 V
5.5
4.8
ns
tw
Pulse duration
1.5 V
63
55
ns
CLR low
3.3 V
0.3 V
7
6.1
5 V
0.5 V
5
4.4
1.5 V
63
55
A, B, C, or D
3.3 V
0.3 V
7
6.1
t
Setup time before CLK
5 V
0.5 V
5
4.4
ns
tsu
Setup time, before CLK
1.5 V
75
66
ns
LOAD
3.3 V
0.3 V
8.4
7.4
5 V
0.5 V
6
5.3
1.5 V
0
0
A, B, C, or D
3.3 V
0.3 V
0
0
th
Hold time after CLK
5 V
0.5 V
0
0
ns
th
Hold time, after CLK
1.5 V
0
0
ns
ENP or ENT
3.3 V
0.3 V
0
0
5 V
0.5 V
0
0
1.5 V
75
66
trec
Recovery time, CLR
before CLK
3.3 V
0.3 V
8.4
7.4
ns
5 V
0.5 V
6
5.3
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
CD54AC161
CD74AC161
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
MAX
MIN
MAX
UNIT
1.5 V
7
8
fmax
3.3 V
0.3 V
64
73
MHz
5 V
0.5 V
90
103
1.5 V
209
190
RCO
3.3 V
0.3 V
6
23.4
6
21
CLK
5 V
0.5 V
4.3
16.7
4.3
15.2
CLK
1.5 V
207
188
Any Q
3.3 V
0.3 V
5.9
23.1
5.9
21
5 V
0.5 V
4.2
16.5
4.2
15
1.5 V
129
117
tpd
ENT
RCO
3.3 V
0.3 V
3.6
14.4
3.7
13.1
ns
5 V
0.5 V
2.6
10.3
2.7
9.4
1.5 V
207
188
Any Q
3.3 V
0.3 V
5.9
23.1
5.9
21
CLR
5 V
0.5 V
4.2
16.5
4.2
15
CLR
1.5 V
207
188
RCO
3.3 V
0.3 V
5.9
23.1
5.9
21
5 V
0.5 V
4.2
16.5
4.2
15
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
66
pF
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239A SEPTEMBER 1998 REVISED APRIL 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50% VCC
tPLH
tPHL
50% VCC
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
R1 = 500
Open
GND
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
Output
Control
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
[
VCC
0 V
50% VCC
VOL + 0.3 V
50% VCC
[
0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC
50% VCC
VOH 0.3 V
VCC
R2 = 500
NOTE: When VCC = 1.5 V, R1 and R2 = 1 k
.
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
VCC
0 V
CLR
Input
CLK
50% VCC
VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
2000, Texas Instruments Incorporated
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