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CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D SEPTEMBER 1998 REVISED DECEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply
D
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
24-mA Output Drive Current
Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The 'AC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP E
Tube
CD74AC74E
CD74AC74E
55
C to 125
C
SOIC
M
Tube
CD74AC74M
AC74M
55
C to 125
C
SOIC M
Tape and reel
CD74AC74M96
AC74M
CDIP F
Tube
CD54AC74F3A
CD54AC74F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
CD54AC74 . . . F PACKAGE
CD74AC74 . . . E OR M PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D SEPTEMBER 1998 REVISED DECEMBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): E package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D SEPTEMBER 1998 REVISED DECEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
TA = 25
C
55
C to
125
C
40
C to
85
C
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
VCC
Supply voltage
1.5
5.5
1.5
5.5
1.5
5.5
V
VCC = 1.5 V
1.2
1.2
1.2
VIH
High-level input voltage
VCC = 3 V
2.1
2.1
2.1
V
VCC = 5.5 V
3.85
3.85
3.85
VCC = 1.5 V
0.3
0.3
0.3
VIL
Low-level input voltage
VCC = 3 V
0.9
0.9
0.9
V
VCC = 5.5 V
1.65
1.65
1.65
VI
Input voltage
0
VCC
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
0
VCC
V
IOH
High-level output current
VCC = 4.5 V to 5.5 V
24
24
24
mA
IOL
Low-level output current
VCC = 4.5 V to 5.5 V
24
24
24
mA
t/
v
Input transition rise or fall rate
VCC = 1.5 V to 3 V
50
50
50
ns/V
t/
v
Input transition rise or fall rate
VCC = 3.6 V to 5.5 V
20
20
20
ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
55
C to
125
C
40
C to
85
C
UNIT
CC
MIN
MAX
MIN
MAX
MIN
MAX
1.5 V
1.4
1.4
1.4
IOH = 50
A
3 V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
VOH
VI = VIH or VIL
IOH = 4 mA
3 V
2.58
2.4
2.48
V
IOH = 24 mA
4.5 V
3.94
3.7
3.8
IOH = 50 mA
5.5 V
3.85
IOH = 75 mA
5.5 V
3.85
1.5 V
0.1
0.1
0.1
IOL = 50
A
3 V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
VOL
VI = VIH or VIL
IOL = 12 mA
3 V
0.36
0.5
0.44
V
IOL = 24 mA
4.5 V
0.36
0.5
0.44
IOL = 50 mA
5.5 V
1.65
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
80
40
A
Ci
10
10
10
pF
Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-
transmission-line drive capability at 85
C and 75-
transmission-line drive capability at 125
C.
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D SEPTEMBER 1998 REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 1.5 V (unless
otherwise noted)
55
C to
125
C
40
C to
85
C
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
9
10
MHz
t
Pulse duration
PRE or CLR low
50
44
ns
tw
Pulse duration
CLK
56
49
ns
t
Setup time
Data
44
39
ns
tsu
Setup time
PRE or CLR inactive
ns
th
Hold time
Data after CLK
0
0
ns
trec
Recovery time, before CLK
CLR
or PRE
34
30
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
55
C to
125
C
40
C to
85
C
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
79
90
MHz
t
Pulse duration
PRE or CLR low
5.6
4.9
ns
tw
Pulse duration
CLK
6.3
5.5
ns
t
Setup time
Data
4.9
4.3
ns
tsu
Setup time
PRE or CLR inactive
ns
th
Hold time
Data after CLK
0
0
ns
trec
Recovery time, before CLK
CLR
or PRE
4.7
4.1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
55
C to
125
C
40
C to
85
C
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
110
125
MHz
t
Pulse duration
PRE or CLR low
4
3.5
ns
tw
Pulse duration
CLK
4.5
3.9
ns
t
Setup time
Data
3.5
3.1
ns
tsu
Setup time
PRE or CLR inactive
ns
th
Hold time
Data after CLK
0
0
ns
trec
Recovery time, before CLK
CLR
or PRE
2.7
2.4
ns
CD54AC74, CD74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS231D SEPTEMBER 1998 REVISED DECEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 1.5 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
55
C to
125
C
40
C to
85
C
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
9
10
MHz
tPLH
CLK
Q
Q
125
114
ns
tPHL
CLK
Q or Q
125
114
ns
tPLH
PRE or CLR
Q or Q
132
120
ns
tPHL
PRE or CLR
Q or Q
144
131
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
55
C to
125
C
40
C to
85
C
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
79
90
MHz
tPLH
CLK
Q
Q
3.5
14
3.6
12.7
ns
tPHL
CLK
Q or Q
3.5
14
3.6
12.7
ns
tPLH
PRE or CLR
Q or Q
3.7
14.7
3.8
13.4
ns
tPHL
PRE or CLR
Q or Q
4
16.1
4.1
14.6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
55
C to
125
C
40
C to
85
C
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
110
125
MHz
tPLH
CLK
Q
Q
2.5
10
2.6
9.1
ns
tPHL
CLK
Q or Q
2.5
10
2.6
9.1
ns
tPLH
PRE or CLR
Q or Q
2.6
10.5
2.7
9.5
ns
tPHL
PRE or CLR
Q or Q
2.9
11.5
3
10.4
ns
operating characteristics, T
A
= 25
C
PARAMETER
TYP
UNIT
Cpd
Power dissipation capacitance
55
pF
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