1
Data sheet acquired from Harris Semiconductor
SCHS145E
Features
Unlimited Input Rise and Fall Times
Exceptionally High Noise Immunity
Typical Propagation Delay: 10ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 37%, N
IH
= 51% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The 'HC132 and 'HCT132 each contain four 2-input NAND
Schmitt Triggers in one package. This logic device utilizes
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The HCT logic family is
functionally pin compatible with the standard LS logic family.
Pinout
CD54HC132, CD54HCT132
(CERDIP)
CD74HC132, CD74HCT132
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC132F3A
-55 to 125
14 Ld CERDIP
CD54HCT132F3A
-55 to 125
14 Ld CERDIP
CD74HC132E
-55 to 125
14 Ld PDIP
CD74HC132M
-55 to 125
14 Ld SOIC
CD74HC132MT
-55 to 125
14 Ld SOIC
CD74HC132M96
-55 to 125
14 Ld SOIC
CD74HCT132E
-55 to 125
14 Ld PDIP
CD74HCT132M
-55 to 125
14 Ld SOIC
CD74HCT132MT
-55 to 125
14 Ld SOIC
CD74HCT132M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
August 1997 - Revised March 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2004, Texas Instruments Incorporated
CD54HC132, CD74HC132,
CD54HCT132, CD74HCT132
High-Speed CMOS Logic
Quad 2-Input NAND Schmitt Trigger
[ /Title
(CD74
HC132
,
CD74
HCT13
2)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
2-Input
NAND
Schmit
2
Functional Diagram
Logic Symbol
TRUTH TABLE
INPUTS
OUTPUT
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
H = High Voltage Level, L = Low Voltage Level
1A
1B
2A
2B
2Y
GND
1
2
3
4
5
6
14
13
12
11
V
CC
4B
3Y
3B
4A
4Y
10
8
7
9
3A
1Y
nA
nB
nY
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
86
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Input Switch Points
(Note 2)
V
T
+
-
-
2
0.7
-
1.5
0.7
1.5
0.7
1.5
V
4.5
1.7
-
3.15
1.7
3.15
1.7
3.15
V
6
2.1
-
4.2
2.1
4.2
2.1
4.2
V
V
T
-
-
-
2
0.3
-
1
0.3
1
0.3
1
V
4.5
0.9
-
2.2
0.9
2.2
0.9
2.2
V
6
1.2
-
3
1.2
3
1.2
3
V
V
H
2
0.2
-
1
0.2
1
0.2
1
V
4.5
0.4
-
1.4
0.4
1.4
0.4
1.4
V
6
0.6
-
1.6
0.6
1.6
0.6
1.6
V
High Level Output
Voltage
CMOS Loads
V
OH
V
T
+ or
V
T
-
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
T
+ or
V
T
-
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
4
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
2
-
20
-
40
A
HCT TYPES
Input Switch Points
(Note 2)
V
T
+
-
-
4.5
1.2
-
1.9
1.2
1.9
1.2
1.9
V
5.5
1.4
-
2.1
1.4
2.1
1.4
2.1
V
V
T
-
-
-
4.5
0.5
-
1.2
0.5
1.2
0.5
1.2
V
5.5
0.6
-
1.4
0.6
1.4
0.6
1.4
V
V
H
-
-
4.5
0.4
-
1.4
0.4
1.4
0.4
1.4
V
5.5
0.4
-
1.5
0.4
1.5
0.4
1.5
V
High Level Output
Voltage
CMOS Loads
-
V
T
+
or
V
T
-
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage CMOS Loads
V
OL
V
T
+
or
V
T
-
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
2
-
20
-
40
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 3)
V
CC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTES:
2. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms
3. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
5
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nB
0.6
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Specifica-
tions table, e.g. 360
A max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay
A, B to Y (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
125
-
156
-
188
ns
4.5
-
-
25
-
31
-
38
ns
6
-
-
21
-
27
-
32
ns
Propagation Delay
A, B to Y
t
TLH
, t
THL
C
L
= 15pF
5
-
10
-
-
-
-
-
pF
Transition Times (Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
-
5
-
30
-
-
-
-
-
pF
HCT TYPES
Propagation Delay
A, B to Y
(Figure 2)
t
PHL
, t
PHL
C
L
= 50pF
4.5
-
-
33
-
41
-
50
ns
Propagation Delay
A, B to Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
13
-
-
-
-
-
pF
Transition Times (Figure 2)
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
-
5
-
30
-
-
-
-
-
pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per gate.
5. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132
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