1
Data sheet acquired from Harris Semiconductor
SCHS151C
Features
Common Select Inputs
Separate Enable Inputs
Buffered inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The
'HC153
and
'HCT153
are
dual
4-
to
1-line
selector/multiplexers that select one of four sources for each
section by the common select inputs, S0 and S1. When the
enable inputs (1E, 2E) are HIGH, the outputs are in the LOW
state.
Pinout
CD54HC153, CD54HCT153
(CERDIP)
CD74HC153, CD74HCT153
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC153F3A
-55 to 125
16 Ld CERDIP
CD54HCT153F3A
-55 to 125
16 Ld CERDIP
CD74HC153E
-55 to 125
16 Ld PDIP
CD74HC153M
-55 to 125
16 Ld SOIC
CD74HC153MT
-55 to 125
16 Ld SOIC
CD74HC153M96
-55 to 125
16 Ld SOIC
CD74HCT153E
-55 to 125
16 Ld PDIP
CD74HCT153M
-55 to 125
16 Ld SOIC
CD74HCT153MT
-55 to 125
16 Ld SOIC
CD74HCT153M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1E
S1
1I
3
1I
2
1I
1
1I
0
GND
1Y
V
CC
S0
2I
3
2I
2
2I
1
2I
0
2Y
2E
September 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC153, CD74HC153,
CD54HCT153, CD74HCT153
High-Speed CMOS Logic
Dual 4- to 1-Line Selector/Multiplexer
[ /Title
(CD74H
C153,
CD74H
CT153)
/Subject
(High
Speed
CMOS
Logic
Dual 4-
Input
2
Functional Diagram
TRUTH TABLE
SELECT INPUTS
DATA INPUTS
ENABLE
OUTPUT
S1
S0
I0
I
1
I
2
I
3
E
Y
X
X
X
X
X
X
H
L
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
X
L
X
L
L
H
L
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
H = High Voltage Level, L = Low Voltage Level, X = Don't Care
NOTE: Select inputs S1 and S0 are common to both sections.
1Y
GND = 8
V
CC
= 16
1I
2
4
3
1I
3
1I
1
5
1I
0
6
SEL/MUX
7
1
14
2
2Y
2I
2
12
13
2I
3
2I
1
11
2I
0
10
SEL/MUX
9
15
1E
S0
S1
2E
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
4
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
Data
0.45
Enable
0.6
Select
1.35
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.
360
A max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay (Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
160
-
200
-
240
ns
S to Y
4.5
-
-
32
-
40
-
48
ns
C
L
=15pF
5
-
13
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
27
-
34
-
41
ns
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
5
I to Y
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
145
-
180
-
220
ns
4.5
-
-
29
-
36
-
44
ns
C
L
=15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
25
-
31
-
38
ns
E to Y
t
PLH,
t
PHL
C
L
= 50pF
2
-
120
-
150
-
180
ns
4.5
-
24
-
30
-
36
ns
C
L
=15pF
5
-
9
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
20
-
26
-
31
ns
Output Transition Time
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
IN
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
45
-
-
-
-
-
pF
HCT TYPES
Propagation Delay (Figure 2)
t
PLH
,
t
PHL
S to Y
C
L
= 50pF
4.5
-
-
34
-
43
-
51
ns
C
L
=15pF
5
-
14
-
-
-
-
ns
I to Y
t
PLH
,
t
PHL
C
L
= 50pF
4.5
-
-
24
-
30
-
36
ns
C
L
=15pF
5
-
9
-
-
-
-
-
ns
I to Y
t
PLH
,
t
PHL
C
L
= 50pF
4.5
-
34
-
43
-
51
ns
C
L
=15pF
5
-
14
-
-
-
-
-
ns
E to Y
t
PLH
,
t
PHL
C
L
= 50pF
4.5
-
-
27
-
34
-
41
ns
C
L
=15pF
5
-
11
-
-
-
-
ns
Output Transition Time
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
IN
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
45
-
-
-
-
-
pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per multiplexer.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications
Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuit and Waveform
FIGURE 1. PROPAGATION DELAY TIMES
t
r
= 6ns
E
I OR S
OUTPUT Y
t
PLH
t
f
= 6ns
90%
V
S
10%
V
S
t
PHL
CD54HC153, CD74HC153, CD54HCT153, CD74HCT153
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