1
Data sheet acquired from Harris Semiconductor
SCHS171D
Features
Buffered Inputs
Typical Propagation Delay ( In to Output ) = 12ns at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The 'HC257 and 'HCT257 are quad 2-input multiplexers
which select four bits of data from two sources under the
control of a common Select Input (S). The Output Enable
input (OE) is active LOW. When OE is HIGH, all of the out-
puts (1Y-4Y) are in the high impedance state regardless of
all other input conditions.
Moving data from two groups of registers to four common
output buses is a common use of the 257. The state of the
Select input determines the particular register from which
the data comes. It can also be used as a function generator.
Pinout
CD54HC257, CD54HCT257
(CERDIP)
CD74HC257, CD74HCT257
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC257F3A
-55 to 125
16 Ld CERDIP
CD54HCT257F3A
-55 to 125
16 Ld CERDIP
CD74HC257E
-55 to 125
16 Ld PDIP
CD74HC257M
-55 to 125
16 Ld SOIC
CD74HC257MT
-55 to 125
16 Ld SOIC
CD74HC257M96
-55 to 125
16 Ld SOIC
CD74HCT257E
-55 to 125
16 Ld PDIP
CD74HCT257M
-55 to 125
16 Ld SOIC
CD74HCT257MT
-55 to 125
16 Ld SOIC
CD74HCT257M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
S
1I
0
1I
1
1Y
2I
0
2I
1
GND
2Y
V
CC
4I
0
4I
1
4Y
3I
0
3I
1
3Y
OE
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC257, CD74HC257,
CD54HCT257, CD74HCT257
High-Speed CMOS Logic Quad 2-Input
Multiplexer with Three-State Non-Inverting Outputs
[ /Title
(CD74
HC257
,
CD74
HCT25
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
2-Input
Multi-
plexer
2
Functional Diagram
3 CIRCUITS IDENTICAL TO CIRCUIT
IN ABOVE DASHED ENCLOSURE
OE
S
4I
1
4I
0
3I
1
3I
0
2I
1
2I
0
1I
1
1I
0
15
1
13
14
10
11
6
5
3
2
12
9
7
4
P
N
4Y
3Y
2Y
1Y
TRUTH TABLE
OUTPUT
ENABLE
SELECT
INPUT
DATA INPUTS
OUTPUT
OE
S
I
0
I
1
Y
H
X
X
X
Z
L
L
L
X
L
L
L
H
X
H
L
H
X
L
L
L
H
X
H
H
H= High Voltage Level
L= Low Voltage Level
X= Don't Care
Z= High Impedance, OFF State
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
70mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
Three-State Leakage
Current
I
OZ
V
IL
or
V
IH
-
6
-
-
0.5
-
5
-
10
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
6
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
to
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
Three-State Leakage
Current
I
OZ
V
IL
or
V
IH
-
5.5
-
-
0.5
-
5
-
10
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
Data
0.95
S
3
OE
0.6
NOTE: Unit Load is
I
CC
limit specified in DC Electrical
Specifications table, e.g., 360
A max at 25
o
C.
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
5
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay
In to Y
t
PLH
, t
PHL
C
L
= 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
C
L
= 15pF
5
12
-
-
-
ns
CL = 50pF
6
-
26
33
38
ns
Propagation Delay
S to Y
t
PLH
, t
PHL
C
L
= 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
C
L
= 15pF
5
14
-
-
-
ns
CL = 50pF
6
-
30
37
45
ns
Propagation Delay
OE to Y
t
PLZ
, t
PHZ
,
t
PZL
, t
PZH
CL = 50pF
2
-
150
190
225
ns
C
L
= 50pF
4.5
-
30
38
45
ns
C
L
= 15pF
5
12
-
-
-
ns
CL = 50pF
6
-
26
33
38
ns
Output Transition Times
t
TLH
, t
THL
C
L
= 50pF
2
-
60
75
90
ns
4.5
-
12
15
18
ns
6
-
10
13
15
ns
Input Capacitance
C
I
-
-
-
10
10
10
pF
Three-State Output
Capacitance
C
O
-
-
-
20
20
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
C
PD
-
5
45
-
-
-
pF
HCT TYPES
Propagation Delay
In to Y
t
PLH
, t
PHL
C
L
= 50pF
4.5
-
33
41
50
ns
C
L
= 15pF
5
13
-
-
-
ns
Propagation Delay
S to Y
t
PZL,
t
PZH
C
L
= 50pF
4.5
-
38
48
57
ns
C
L
= 15pF
5
12
-
-
-
ns
Propagation Delay
OE to Y
t
PLZ
, t
PHZ
C
L
= 50pF
4.5
-
30
38
45
ns
C
L
= 15pF
5
16
-
-
-
ns
Output Transition Times
t
TLH
, t
THL
C
L
= 50pF
4.5
-
12
15
18
ns
Input Capacitance
C
I
-
-
-
10
10
10
pF
Three-State Output
Capacitance
C
O
-
-
-
20
20
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
C
PD
-
5
45
-
-
-
pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per multiplexer.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
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