1
Data sheet acquired from Harris Semiconductor
SCHS173
Features
Buffered Inputs and Outputs
Four Operating Modes
Typical Propagation Delay of 15ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The Harris CD74HC259 and CD74HCT259 Addressable
Latch features the low-power consumption associated with
CMOS circuitry and has speeds comparable to low-power
Schottky.
This latches three active modes and one reset mode. When
both the Latch Enable (LE) and Master Reset (MR) inputs are
low (8-line Demultiplexer mode) the output of the addressed
latch follows the Data input and all other outputs are forced
low. When both MR and LE are high (Memory Mode), all
outputs are isolated from the Data input, i.e., all latches hold
the last data presented before the LE transition from low to
high. A condition of LE low and MR high (Addressable Latch
mode) allows the addressed latch's output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when LE is high and MR is low.
Pinout
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
PKG.
NO.
CD74HC259E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT259E
-55 to 125
16 Ld PDIP
E16.3
CD74HC259M
-55 to 125
16 Ld SOIC
M16.15
CD74HCT259M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
Q0
Q1
Q2
GND
Q3
V
CC
LE
D
Q7
Q6
Q5
Q4
MR
November 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
File Number
1727.1
CD74HC259,
CD74HCT259
High Speed CMOS Logic
8-Bit Addressable Latch
[ /Title
(CD74
HC259
,
CD74
HCT25
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)
2
Functional Diagram
1
2
3
14
15
13
4
5
6
7
10
12
11
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MR
LE
8
LATCHES
1-OF-8
DECODER
D
A
2
A
1
A
0
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS
OUTPUT OF
ADDRESS
LATCH
EACH OTHER
OUTPUT
FUNCTION
MR
LE
H
L
D
Q
io
Addressable
Latch
H
H
Q
io
Q
io
Memory
L
L
D
L
8-Line
Demultiplexer
L
H
L
L
Reset
NOTE:
H
= High Voltage Level
L
= Low Voltage Level
D
= The level at the data input
Q
io
= The level of Q
i
(i = 0, 1...7, as appropriate) before the indicated
steady-state input conditions were established.
LATCH SELECTION TABLE
SELECT INPUTS
LATCH
ADDRESSED
A2
A1
A0
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
CD74HC259, CD74HCT259
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
25mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD74HC259, CD74HCT259
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE: For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
A0 - A2, LE
1.5
D
1.2
MR
0.75
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
HC TYPES
Pulse Width
t
WL
LE
2
70
-
-
90
-
-
105
-
-
ns
4.5
14
-
-
18
-
-
21
-
-
ns
6
12
-
-
15
-
-
18
-
-
ns
CD74HC259, CD74HCT259
5
MR
t
WL
2
70
-
-
90
-
-
105
-
-
ns
4.5
14
-
-
18
-
-
21
-
-
ns
6
12
-
-
15
-
-
18
-
-
ns
Setup Time
t
SU
D to LE
A to LE
2
80
-
-
100
-
-
120
-
-
ns
4.5
16
-
-
20
-
-
24
-
-
ns
6
14
-
-
17
-
-
20
-
-
ns
Hold Time
t
H
D to LE
A to LE
2
0
-
-
0
-
-
0
-
-
ns
4.5
0
-
-
0
-
-
0
-
-
ns
6
0
-
-
0
-
-
0
-
-
ns
HCT TYPES
Pulse Width
LE
MR
t
WL
4.5
18
-
-
23
-
-
27
-
-
ns
Setup Time
D to LE
A to LE
t
SU
4.5
17
-
-
21
-
-
26
-
-
ns
Hold Time
D to LE
A to LE
t
H
4.5
0
-
-
0
-
-
0
-
-
ns
Prerequisite for Switching Specifications
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay
t
PHL
C
L
= 50pF
D to Q
2
-
-
185
-
230
-
280
ns
4.5
-
-
37
-
46
-
56
ns
C
L
= 15pF
5
-
15
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
31
-
39
-
48
ns
LE to Q
t
PHL
C
L
= 50pF
2
-
-
170
-
215
-
255
ns
4.5
-
-
34
-
43
-
51
ns
C
L
= 15pF
5
-
14
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
29
-
37
-
43
ns
CD74HC259, CD74HCT259
6
A to Q
t
PHL
C
L
= 50pF
2
-
-
185
-
230
-
280
ns
4.5
-
-
37
-
46
-
56
ns
C
L
= 15pF
5
-
15
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
31
-
39
-
48
ns
MR to Q
t
PHL,
t
PLH
C
L
= 50pF
2
-
-
155
-
195
-
235
ns
4.5
-
-
31
-
39
-
47
ns
C
L
= 15pF
5
-
13
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
40
ns
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
C
L
= 15pF
5
-
21
-
-
-
-
-
pF
Input Capacitance
C
I
C
L
= 50pF
-
10
-
10
-
10
-
10
pF
HCT TYPES
Propagation Delay
t
PHL,
t
PLH
D to Q
C
L
= 50pF
4.5
-
-
39
-
49
-
59
ns
C
L
= 15pF
5
-
16
-
-
-
-
-
ns
LE to Q
C
L
= 50pF
4.5
-
-
38
-
48
-
57
ns
C
L
= 15pF
5
-
16
-
-
-
-
-
ns
A to Q
C
L
= 50pF
4.5
-
-
41
-
51
-
61
ns
C
L
= 15pF
5
-
17
-
-
-
-
-
ns
MR to Q
C
L
= 50pF
4.5
-
-
39
-
49
-
59
ns
C
L
= 15pF
5
-
16
-
-
-
-
-
ns
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
C
L
= 15pF
5
-
22
-
-
-
-
-
pF
Input Capacitance
C
I
C
L
= 50pF
-
10
-
10
-
10
-
10
pF
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per package.
5. P
D
= C
PD
V
CC
2
f
i
+
C
L
V
CC
2
f
O
where f
i
= Input Frequency, f
O
= Output Frequency, C
L
= Output Load Capacitance,
V
CC
= Supply Voltage.
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD74HC259, CD74HCT259
7
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
t
r
C
L
t
f
C
L
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
10%
1.3V
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
1.3V
t
H(H)
1.3V
CD74HC259, CD74HCT259
8
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE:
Open drain waveforms t
PLZ
and t
PZL
are the same as those for three-state shown on the left. The test circuit is Output R
L
= 1k
to
V
CC
, C
L
= 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
50%
10%
90%
GND
V
CC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
r
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
6ns
t
f
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
V
CC
FOR t
PLZ
AND t
PZL
GND FOR t
PHZ
AND t
PZH
OUTPUT
R
L
= 1k
C
L
50pF
CD74HC259, CD74HCT259
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