ChipFind - документация

Электронный компонент: CD74HC365M

Скачать:  PDF   ZIP
1
Data sheet acquired from Harris Semiconductor
SCHS180C
Features
Buffered Inputs
High Current Bus Driver Outputs
Typical Propagation Delay t
PLH
, t
PHL
= 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The 'HC365, 'HCT365, and 'HC366 silicon gate CMOS three-
state buffers are general purpose high-speed non-inverting
and inverting buffers. They have high drive current outputs
which enable high speed operation even when driving large
bus capacitances. These circuits possess the low power
dissipation of CMOS circuitry, yet have speeds comparable to
low power Schottky TTL circuits. Both circuits are capable of
driving up to 15 low power Schottky inputs.
The 'HC365 and 'HCT365 are non-inverting buffers, whereas
the 'HC366 is an inverting buffer. These devices have two
three-state control inputs (OE1 and OE2) which are NORed
together to control all six gates.
The 'HCT365 logic families are speed, function and pin
compatible with the standard LS logic family.
Pinout
CD54HC365, CD54HCT365, CD54HC366
(CERDIP)
CD74HC365, CD74HCT365, CD74HC366
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC365F3A
-55 to 125
16 Ld CERDIP
CD54HC366F3A
-55 to 125
16 Ld CERDIP
CD54HCT365F3A
-55 to 125
16 Ld CERDIP
CD74HC365E
-55 to 125
16 Ld PDIP
CD74HC365M
-55 to 125
16 Ld SOIC
CD74HC365MT
-55 to 125
16 Ld SOIC
CD74HC365M96
-55 to 125
16 Ld SOIC
CD74HC366E
-55 to 125
16 Ld PDIP
CD74HC366M
-55 to 125
16 Ld SOIC
CD74HC366M96
-55 to 125
16 Ld SOIC
CD74HCT365E
-55 to 125
16 Ld PDIP
CD74HCT365M
-55 to 125
16 Ld SOIC
CD74HCT365MT
-55 to 125
16 Ld SOIC
CD74HCT365M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and real. The suffix T denotes a small-quantity reel of
250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
(1Y) 1Y
2A
(2Y) 2Y
3A
GND
(3Y) 3Y
V
CC
6A
6Y (6Y)
5A
5Y (5Y)
4A
4Y (4Y)
OE2
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54/74HC365, CD54/74HCT365,
CD54/74HC366
High Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
[ /Title
(CD74
HC365
,
CD74
HCT36
5,
CD74
HC366
,
CD74
HCT36
6)
/Sub-
ject
(High
Speed
2
Functional Diagrams
HC365, HCT365
HC366
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
V
CC
6A
6Y
5A
5Y
4A
4Y
OE2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OE1
1A
1Y
2A
2Y
3A
GND
3Y
V
CC
6A
6Y
5A
5Y
4A
4Y
OE2
TRUTH TABLE
INPUTS
OUTPUTS
(Y)
OE1
OE2
A
HC/HCT365
HC366
L
L
L
L
H
L
L
H
H
L
X
H
X
Z
Z
H
X
X
Z
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance (OFF) State
CD54/74HC365, CD54/74HCT365, CD54/74HC366
3
Logic Diagram
NOTE: Inverter not included in HC/HCT365.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSE
SHOWN, i.e., 1Y, 2Y, ETC.)
4
2A
2Y
5
6
3A
3Y
7
10
4A
4Y
9
12
5A
5Y
11
14
6A
6Y
13
OE1
1
15
OE2
ONE OF SIX IDENTICAL CIRCUITS
V
CC
3
1Y
GND
8
(NOTE)
2
1A
16
CD54/74HC365, CD54/74HCT365, CD54/74HC366
4
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD54/74HC365, CD54/74HCT365, CD54/74HC366
5
Three-State Leakage
Current
I
OZ
V
IL
or
V
IH
V
O
=
V
CC
or
GND
6
-
-
0.5
-
5.0
-
10
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
to
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 2)
I
CC
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
Three-State Leakage
Current
I
OZ
V
IL
or
V
IH
V
O
=
V
CC
or
GND
5.5
-
-
0.5
-
5.0
-
10
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
OE1
0.6
All Others
0.55
NOTE: Unit Load is
I
CC
limit specified in DC Electrical
Specifications table, e.g., 360
A max at 25
o
C.
Switching Specifications - HC/HCT365
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO
125
o
C
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay,
Data to Outputs
HC/HCT365
t
PLH
, t
PHL
C
L
= 50pF
2
-
105
130
160
ns
4.5
-
21
26
32
ns
6
-
18
22
27
ns
C
L
= 15pF
5
8
-
-
-
ns
CD54/74HC365, CD54/74HCT365, CD54/74HC366