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Электронный компонент: CD74HC390M

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1
Data sheet acquired from Harris Semiconductor
SCHS185C
Features
Two BCD Decade or Bi-Quinary Counters
One Package Can Be Configured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
Two Master Reset Inputs to Clear Each Decade
Counter Individually
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HCT390
(CERDIP)
CD74HC390, CD74HCT390
(PDIP, SOIC)
TOP VIEW
Description
The CD74HC390 and 'HCT390 dual 4-bit decade ripple
counters are high-speed silicon-gate CMOS devices and are
pin compatible with low-power Schottky TTL (LSTTL). These
devices are divided into four separately clocked sections.
The counters have two divide-by-2 sections and two divide-
by-5 sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a com-
mon master reset (nMR). If the two master reset inputs (1MR
and 2MR) are used to simultaneously clear all 8 bits of the
counter, a number of counting configurations are possible
within one package. The separate clock inputs (nCP0 and
nCP1) of each section allow ripple counter or frequency divi-
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.
Each section is triggered by the High-to-Low transition of the
input pulses (nCP0 and nCP1).
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
input and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identified by the "1" and "2"
prefixes in the pin configuration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1CP0
1MR
1Q
0
1CP1
1Q
1
1Q
2
GND
1Q
3
V
CC
2MR
2Q0
2CP1
2Q
1
2Q
2
2Q
3
2CP0
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HCT390F3A
-55 to 125
16 Ld CERDIP
CD74HC390E
-55 to 125
16 Ld PDIP
CD74HC390M
-55 to 125
16 Ld SOIC
CD74HC390MT
-55 to 125
16 Ld SOIC
CD74HC390M96
-55 to 125
16 Ld SOIC
CD74HCT390E
-55 to 125
16 Ld PDIP
CD74HCT390M
-55 to 125
16 Ld SOIC
CD74HCT390MT
-55 to 125
16 Ld SOIC
CD74HCT390M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
September 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD74HC390,
CD54HCT390, CD74HCT390
High-Speed CMOS Logic
Dual Decade Ripple Counter
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
2
Functional Diagram
4 (12)
5 (11)
7 (9)
nQ
3
nQ
1
nCP1
5
nCP0
2 (14)
1 (15)
3 (13)
nQ
0
nMR
2
COUNTER
COUNTER
6 (10)
nQ
2
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS
ACTION
CP
MR
L
No Change
L
Count
X
H
All Qs Low
H = High Voltage Level, L = Low Voltage Level, X = Don't Care,
= Transition from Low to High Level,
= Transition from High to Low.
BCD COUNT SEQUENCE FOR 1/2 THE 390
COUNT
OUTPUTS
Q0
Q1
Q2
Q3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
Output nQ0 connected to nCP1 with counter input on nCP0.
B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390
COUNT
OUTPUTS
Q0
Q1
Q2
Q3
0
L
L
L
L
1
L
H
L
L
2
L
L
H
L
3
L
H
H
L
4
L
L
L
H
5
H
L
L
L
6
H
H
H
L
7
H
L
H
L
8
H
H
H
L
9
H
L
L
H
Output nQ3 connected to nCP0 with counter input on nCP1.
CD74HC390, CD54HCT390, CD74HCT390
3
Logic Diagram
nQ
0
nQ
2
nQ
3
3(13)
6(10)
7(9)
Q
R
Q
R
Q
R
Q
R
nQ
1
5(11)
V
CC
= 16
GND = 8
4(12)
nCP1
1(15)
nCP0
2(14)
nMR
CD74HC390, CD54HCT390, CD74HCT390
4
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD74HC390, CD54HCT390, CD74HCT390
5
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
nCP0
0.45
nCP1, MR
0.6
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
Prerequisite for Switching Specifications
CHARACTERISTIC
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Maximum Clock
Frequency
f
MAX
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
24
-
20
-
MHz
6
35
-
-
28
-
24
-
MHz
Clock Pulse Width,
nCP0, nCP1
t
W
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
CD74HC390, CD54HCT390, CD74HCT390