1
Data sheet acquired from Harris Semiconductor
SCHS200D
Features
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f
MAX
= 50MHz at V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Description
The 'HC4017 is a high speed silicon gate CMOS 5-stage
Johnson counter with 10 decoded outputs. Each of the
decoded outputs is normally low and sequentially goes high
on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes from high to low, and can be used in
conjunction with the CLOCK ENABLE (CE) to cascade
several stages. The CLOCK ENABLE input disables
counting when in the high state. A RESET (MR) input is also
provided which when taken high sets all the decoded
outputs, except "0", low.
The device can drive up to 10 low power Schottky equivalent
loads.
Pinout
CD54HC4017 (CERDIP)
CD74HC4017 (PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4017F3A
-55 to 125
16 Ld CERDIP
CD74HC4017E
-55 to 125
16 Ld PDIP
CD74HC4017M
-55 to 125
16 Ld SOIC
CD74HC4017MT
-55 to 125
16 Ld SOIC
CD74HC4017M96
-55 to 125
16 Ld SOIC
CD74HC4017NSR
-55 to 125
16 Ld SOP
CD74HC4017PW
-55 to 125
16 Ld TSSOP
CD74HC4017PWR
-55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
5
1
0
2
6
7
GND
3
V
CC
CP
CE
TC
9
4
8
MR
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4017, CD74HC4017
High-Speed CMOS Logic
Decade Counter/Divider with 10 Decoded Outputs
[ /Title
(CD74
HC401
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Decade
Counte
2
Functional Diagram
TRUTH TABLE
CP
CE
MR
OUTPUT STATE
L
X
L
No Change
X
H
L
No Change
X
X
H
"0" = H, "1"-"9" = L
L
L
Increments Counter
X
L
No Change
X
L
No Change
H
L
Increments Counter
H = High Level
L = Low Level
= High to Low Transition
= Low to High Transition
X = Don't Care.
If n < 5 TC = H, Otherwise = L
3
2
4
7
1
6
5
10
0
1
2
3
4
5
6
7
14
13
15
CLOCK
CLOCK
MASTER
9
12
11
8
9
TERMINAL
COUNT
RESET
ENABLE
DECODED DECIMAL OUT
CD54HC4017, CD74HC4017
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance,
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD54HC4017, CD74HC4017
4
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Maximum Clock
Frequency
f
MAX
-
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
35
-
20
-
MHz
6
35
-
-
49
-
23
-
MHz
CP Pulse Width
t
W
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
MR Pulse Width
t
W
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Set-up Time,
CE to CP
t
SU
-
2
75
-
-
95
-
110
-
ns
4.5
15
-
-
19
-
22
-
ns
6
13
-
-
16
-
19
-
ns
Hold Time,
CE to CP
t
H
-
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
MR Removal Time
t
REM
-
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Propagation Delay
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
230
-
290
-
345
ns
CP to any Dec. Out
C
L
= 50pF
4.5
-
-
46
-
58
-
69
ns
C
L
= 15pF
5
-
19
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
39
-
49
-
59
ns
CP to TC
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
230
-
290
-
345
ns
C
L
= 50pF
4.5
-
-
46
-
58
-
69
ns
C
L
= 15pF
5
-
19
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
39
-
49
-
59
ns
CE to any Dec. Out
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
250
-
315
-
375
ns
C
L
= 50pF
4.5
-
-
50
-
63
-
75
ns
C
L
= 15pF
5
-
21
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
43
-
54
-
64
ns
CE to TC
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
250
-
315
-
375
ns
C
L
= 50pF
4.5
-
-
50
-
63
-
75
ns
C
L
= 15pF
5
-
21
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
43
-
54
-
64
ns
CD54HC4017, CD74HC4017
5
MR to any Dec. Out
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
230
-
290
-
345
ns
C
L
= 50pF
4.5
-
-
46
-
58
-
69
ns
C
L
= 15pF
5
-
19
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
39
-
49
-
59
ns
MR to TC
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
230
-
290
-
345
ns
C
L
= 50pF
4.5
-
-
46
-
58
-
69
ns
C
L
= 15pF
5
-
19
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
39
-
49
-
59
ns
Transition Time TC, Dec. Out
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
C
L
= 50pF
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
IN
C
L
= 50pF
-
-
-
10
-
10
-
10
pF
Maximum CP Frequency
f
MAX
C
L
= 15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation Capacitance
(Notes 2, 3)
C
PD
C
L
= 15pF
5
-
39
-
-
-
-
-
pF
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per package.
3. P
D
= V
CC
2
f
i
C
L
V
CC
2
fo where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
= supply voltage.
Switching Specifications
Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
CD54HC4017, CD74HC4017
6
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
Timing Diagrams
FIGURE 4.
FIGURE 5.
Test Circuits and Waveforms
(Continued)
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
C
L
C
L
P
N
P
N
P N
P
N
D
C
L
Q
C
FF DETAIL
C
L
C
L
C
L
C
L
C
L
C
L
Q
R
CLOCK
MASTER
RESET
CLOCK
ENABLE
"0"
"1"
"2"
"3"
"4"
"5"
"6"
"7"
"8"
"9"
TERMINAL
COUNT
0
1
2
3
4
5
6
7
8
9
0
1
2
CD54HC4017, CD74HC4017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
8601101EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
CD54HC4017F3A
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
CD74HC4017E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4017EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4017M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4017PWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
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26-Sep-2005
Addendum-Page 1
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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