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Электронный компонент: CD74HC4050M

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1
Data sheet acquired from Harris Semiconductor
SCHS205I
Features
Typical Propagation Delay: 6ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
High-to-Low Voltage Level Converter for up to V
l
= 16V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . 55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
Pinout
CD54HC4049, CD54HC4050
(CERDIP)
CD74HC4049, CD74HC4050
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Description
The 'HC4049 and 'HC4050 are fabricated with high-speed
silicon gate technology. They have a modified input
protection structure that enables these parts to be usedas
logic level translators which convert high-level logic to a low-
level logic while operating off the low-level logic supply. For
example, 15-V input pulse levels can be down-converted to
0-V to 5-V logic levels. The modified input protection
structure protects the input from negative electrostatic
discharge. These parts also can be used as simple buffers
or inverters without level translation. The 'HC4049 and
'HC4050 are enhanced versions of equivalent CMOS types.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V
CC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
4049
4050
4050
4049
V
CC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4049F3A
55 to 125
16 Ld CERDIP
CD54HC4050F3A
55 to 125
16 Ld CERDIP
CD74HC4049E
55 to 125
16 Ld PDIP
CD74HC4049M
55 to 125
16 Ld SOIC
CD74HCT4050MT
55 to 125
16 Ld SOIC
CD74HC4049M96
55 to 125
16 Ld SOIC
CD74HC4049NSR
55 to 125
16 Ld SOP
CD74HC4049PW
55 to 125
16 Ld TSSOP
CD74HC4049PWR
55 to 125
16 Ld TSSOP
CD74HC4049PWT
55 to 125
16 Ld TSSOP
CD74HC4050E
55 to 125
16 Ld PDIP
CD74HC4050M
55 to 125
16 Ld SOIC
CD74HC4050MT
55 to 125
16 Ld SOIC
CD74HC4050M96
55 to 125
16 Ld SOIC
CD74HC4050NSR
55 to 125
16 Ld SOP
CD74HC4050PW
55 to 125
16 Ld TSSOP
CD74HC4050PWR
55 to 125
16 Ld TSSOP
CD74HC4050PWT
55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
February 1998 - Revised February 2005
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2005,Texas Instruments Incorporated
CD54HC4049, CD74HC4049,
CD54HC4050, CD74HC4050
High-Speed CMOS Logic
Hex Buffers, Inverting and Non-Inverting
[ /Title
(CD74H
C4049,
CD74H
C4050)
/Sub-
ject
(High
Speed
CMOS
Logic
Hex
2
Functional Diagram
1A
1Y
2Y
3A
3Y
GND
1
2
3
4
5
6
16
14
13
12
NC
5A
4Y
5Y
6A
NC
11
9
7
10
4A
2A
V
CC
8
15
6Y
4050
4049
4049
4050
1Y
2Y
3Y
6Y
NC
5Y
Logic Diagrams
HC4049
HC4050
A
Y
A
Y
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to 16V
DC Input Diode Current, I
IK
For V
I
< 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
DC Output Diode Current, I
OK
For V
O
< 0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> 0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . .55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input Voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 15V
DC Output Voltage, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance,
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . 65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
V
CC
V
l
+7V
+16V
VOLTAGE
RELATIONSHIPS
MAXIMUM LIMITS
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
40
o
C TO 85
o
C
55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
0.02
2
1.9
-
-
1.9
-
1.9
-
V
0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
4
4.5
3.98
-
-
3.84
-
3.7
-
V
5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
15
-
6
-
-
0.5
-
5
-
5
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
2
-
20
-
40
A
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
40
o
C TO 85
o
C
55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
40
o
C TO
85
o
C
55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
85
-
105
-
130
ns
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
C
L
= 15pF
5
-
6
-
-
-
-
-
ns
Transition Times (Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 2, 3)
C
PD
-
5
-
35
-
-
-
-
-
pF
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per gate.
3. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Test Circuit and Waveform
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-8681901EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
5962-8682001EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
CD54HC4049F3A
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
CD54HC4050F3A
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
CD74HC4049E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4049M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4049PWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4050EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
CD74HC4050M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4050MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 1