1
Data sheet acquired from Harris Semiconductor
SCHS216D
Features
Positive or Negative Edge Triggering
Synchronous Internal Carry Propagation
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The CD74HC4518 is a dual BCD up-counter. The 'HC4520
and CD74HCT4520 are dual binary up-counters. Each
device consists of two independent internally synchronous
4-stage counters. The counter stages are D-type flip-flops
having interchangeable CLOCK and ENABLE lines for
incrementing on either the positive-going or the negative-
going transition of CLOCK. The counters are cleared by high
levels on the MASTER RESET lines. The counter can be
cascaded in the ripple mode by connecting Q
3
to the
ENABLE input of the subsequent counter while the CLOCK
input of the latter is held low.
Pinout
CD54HC4520
(CERDIP)
CD74HC4518
(PDIP)
CD74HC4520, CD74HCT4520,
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4520F3A
-55 to 125
16 Ld CERDIP
CD74HC4518E
-55 to 125
16 Ld PDIP
CD74HC4520E
-55 to 125
16 Ld PDIP
CD74HC4520M
-55 to 125
16 Ld SOIC
CD74HC4520MT
-55 to 125
16 Ld SOIC
CD74HC4520M96
-55 to 125
16 Ld SOIC
CD74HCT4520E
-55 to 125
16 Ld PDIP
CD74HCT4520M
-55 to 125
16 Ld SOIC
CD74HCT4520MT
-55 to 125
16 Ld SOIC
CD74HCT4520M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1CP
1E
1Q
0
1Q
1
1Q
2
1Q
3
GND
1MR
V
CC
2Q
3
2Q
2
2Q
1
2Q
0
2E
2CP
2MR
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD74HC4518, CD54HC4520,
CD74HC4520, CD74HCT4520
High-Speed CMOS Logic
Dual Synchronous Counters
[ /Title
(CD74
HC451
8,
CD74
HC452
0,
CD74
HCT45
20)
/Sub-
ject
2
Functional Diagram
TRUTH TABLE
CP
E
MR
OUTPUT STATE
H
L
Increment Counter
L
L
Increment Counter
X
L
No Change
X
L
No Change
L
L
No Change
H
L
No Change
X
X
H
Q
0
thru Q
3
= L
H
= High State.
L
= Low State.
= High-to-Low Transition.
= Low-to-High Transition.
X
= Don't Care.
1CP
1Q
2
5
6
1Q
3
1Q
1
4
1Q
0
3
1
1E
2
CL
R
1MR
7
10/
16
2CP
2Q
2
13
14
2Q
3
2Q
1
12
2Q
0
11
9
2E
10
CL
R
2MR
15
10/
16
GND = 8
V
CC
= 16
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
4
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to 5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to 5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 2)
V
CC
-2.1
-
4.5 to 5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
MR
1.2
CP
0.25
ENABLE
0.5
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Maximum Clock
Frequency
f
MAX
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
24
-
20
-
MHz
6
35
-
-
28
-
24
-
MHz
CP Pulse Width
t
W
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
MR Pulse Width
t
W
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
5
Set-up Time,
Enable to CP
t
SU
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Removal Time,
MR to CP
t
REM
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
Set-up Time,
CP to Enable
t
SU
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Removal Time,
MR to Enable
t
REM
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
25
-
-
20
-
17
-
MHz
Clock Pulse Width
t
W
4.5
20
-
-
25
-
30
-
ns
MR Pulse Width
t
W
4.5
20
-
-
25
-
30
-
ns
Set-up Time,
Enable to CP
t
SU
4.5
16
-
-
20
-
24
-
ns
Removal Time,
MR tp Enable
t
REM
4.5
0
-
-
0
-
0
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
240
-
300
-
360
ns
CP to Q
n
C
L
= 50pF
4.5
-
-
48
-
60
-
72
ns
C
L
= 15pF
5
-
20
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
41
-
51
-
61
ns
Enable to Q
n
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
240
-
300
-
360
ns
C
L
= 50pF
4.5
-
-
48
-
60
-
72
ns
C
L
= 15pF
5
-
20
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
41
-
51
-
61
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
150
-
190
-
225
ns
C
L
= 50pF
4.5
-
-
30
-
38
-
45
ns
C
L
= 15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
38
ns
Output Transition Time
t
THL
, t
TLH
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
CL = 50pF
6
13
16
19
ns
Input Capacitance
C
IN
C
L
= 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
f
MAX
CL = 15pF
5
60
MHz
Power Dissipation Capacitance
(Note 3, 4)
C
PD
C
L
= 15pF
5
-
33
-
-
-
-
-
pF
Prerequisite for Switching Specifications
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
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