CD74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCHS353 - JANUARY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
8-Bit Serial-In, Parallel-Out Shift
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 14 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Shift Register Has Direct Clear
description/ordering information
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and
storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial
output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - E
Tube of 25
CD74HC595E
CD74HC595E
SOIC - DW
Tube of 40
CD74HC595DW
HC595M
SOIC - DW
Reel of 2000
CD74HC595DWR
HC595M
Tube of 40
CD74HC595M
-55
C to 125
C
SOIC - M
Reel of 2500
CD74HC595M96
HC595M
-55 C to 125 C
SOIC - M
Reel of 250
CD74HC595MT
HC595M
SOP - NS
Reel of 2000
CD74HC595NSR
HC595M
SSOP - SM
Tube of 80
CD74HC595SM
HJ595
SSOP - SM
Reel of 2000
CD74HC595SM96
HJ595
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DW, E, M, NS, OR SM PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
CD74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCHS353 - JANUARY 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
FUNCTION
X
X
X
X
H
Outputs QA-QH are disabled.
X
X
X
X
L
Outputs QA-QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
X
Shift-register data is stored in the storage register.
CD74HC595
8 BIT SHIFT REGISTERS
WITH 3 STATE OUTPUT REGISTERS
SCHS353 - JANUARY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): E package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
57
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SM package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
V
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
ns
t/
v
Input transition rise/fall time
VCC = 6 V
400
ns
TA
Operating free-air temperature
-55
125
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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