CDCV850, CDCV850I
2.5 V PHASE LOCK LOOP CLOCK DRIVER
WITH 2 LINE SERIAL INTERFACE
SCAS647B - OCTOBER 2000 - REVISED DECEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D
Spread Spectrum Clock Compatible
D
Operating Frequency: 60 to 140 MHz
D
Low Jitter (cyc-cyc):
75 ps
D
Distributes One Differential Clock Input to
Ten Differential Outputs
D
Two-Line Serial Interface Provides Output
Enable and Functional Control
D
Outputs Are Put Into a High-Impedance
State When the Input Differential Clocks
Are <20 MHz
D
48-Pin TSSOP Package
D
Consumes <250-
A Quiescent Current
D
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
description
The CDCV850 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are con-
trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,
SCLK), and the analog power input (AV
DD
). A two-line serial interface can put the individual output clock pairs
in a high-impedance state. When the AV
DD
terminal is tied to GND, the PLL is turned off and bypassed for test
purposes.
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 k
).
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in
applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as changes to various 2-line serial registers that
affect the PLL. The CDCV850 is characterized for both commercial and industrial temperature ranges.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y0
Y0
V
DDQ
Y1
Y1
GND
GND
Y2
Y2
V
DDQ
SCLK
CLK
CLK
V
DDI
AV
DD
AGND
GND
Y3
Y3
V
DDQ
Y4
Y4
GND
GND
Y5
Y5
V
DDQ
Y6
Y6
GND
GND
Y7
Y7
V
DDQ
SDATA
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y8
Y8
V
DDQ
Y9
Y9
GND
DGG PACKAGE
(TOP VIEW)
CDCV850, CDCV850I
2.5 V PHASE LOCK LOOP CLOCK DRIVER
WITH 2 LINE SERIAL INTERFACE
SCAS647B - OCTOBER 2000 - REVISED DECEMBER 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
TA
TSSOP (DGG)
0
C to 85
C
CDCV850DGG
- 40
C to 85
C
CDCV850IDGG
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
PLL
GND
L
H
L
H
L
H
Bypassed/Off
GND
H
L
H
L
H
L
Bypassed/Off
2.5 V (nom)
L
H
L
H
L
H
On
2.5 V (nom)
H
L
H
L
H
L
On
2.5 V (nom)
<20 MHz
<20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Off
Each output pair (except FBOUT, FBOUT) can be put into a high-impedance state through the 2-line
serial interface.
functional block diagram
30
29
40
39
43
44
47
46
23
22
19
20
9
10
6
5
3
2
26
27
33
32
13
36
14
35
PLL
AV
DD
16
37
12
V
DDI
Interface
Logic
10
CLK
FBIN
FBIN
CLK
SDATA
SCLK
2-Line Serial
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
CDCV850, CDCV850I
2.5 V PHASE LOCK LOOP CLOCK DRIVER
WITH 2 LINE SERIAL INTERFACE
SCAS647B - OCTOBER 2000 - REVISED DECEMBER 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
17
Ground for 2.5
-
V analog supply
AVDD
16
2.5
-
V analog supply
CLK, CLK
13, 14
I
Differential clock input
FBIN, FBIN
35, 36
I
Feedback differential clock input
FBOUT, FBOUT
32, 33
O
Feedback differential clock output
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
SCLK
12
I
Clock input for 2-line serial interface
SDATA
37
I/O
Data input/output for 2-line serial interface
VDDQ
4, 11, 21,
28, 34, 38,
45
2.5-V supply
VDDI
15
I
2.5-V or 3.3-V supply for 2-line serial interface
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
Buffered output copies of input clock, CLK
Y[0:9]
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Buffered output copies of input clock, CLK
CDCV850, CDCV850I
2.5 V PHASE LOCK LOOP CLOCK DRIVER
WITH 2 LINE SERIAL INTERFACE
SCAS647B - OCTOBER 2000 - REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: V
DDQ,
AV
DD
-0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
DDI
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range:
V
I
(except SCLK and SDATA) (see Notes 1 and 2)
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . .
V
I
(SCLK, SDATA) (see Notes 1 and 2)
0.5 V to V
DDI
+ 0.5 V
. . . . . . . . . . . . . . . . . . .
Output voltage range: V
O
(except SDATA) (see Notes 1 and 2)
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . . . . . . . . . . .
V
O
(SDATA) (see Notes 1 and 2)
0.5 V to V
DDQ
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
89
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
TYP
MAX
UNIT
Supply voltage
VDDQ, AVDD
2.3
2.7
V
Supply voltage
VDDI (see Note 5)
2.3
3.6
V
CLK, CLK, HCSL Buffer only
0
0.24
Low level input voltage, VIL
CLK, CLK
-0.3
VDDQ - 0.4
V
Low level input voltage, VIL
FBIN, FBIN
VDDQ/2 - 0.18
V
SDATA, SCLK
0.3
VDDI
CLK, CLK, HCSL Buffer only
0.66
0.71
High level input voltage, VIH
CLK, CLK
0.4
VDDQ + 0.3
V
High level input voltage, VIH
FBIN, FBIN
VDDQ/2 + 0.18
V
SDATA, SCLK
0.7
VDDI
DC input signal voltage (see Note 6)
0.3
VDDQ + 0.3
V
Differential input signal voltage, VID (see Note 7)
DC
CLK, FBIN
0.36
VDDQ + 0.6
V
Differential input signal voltage, VID (see Note 7)
AC
CLK, FBIN
0.2
VDDQ + 0.6
V
Input differential pair cross-voltage, VIX (see Note 8)
0.45
(VIH-VIL)
0.55
(VIH-VIL)
V
High-level output current, IOH
-12
mA
Low-level output current, IOL
12
V
Low-level output current, IOL
SDATA
3
mA
Input slew rate, SR (see Figure 8)
1
4
V/ns
SSC modulation frequency
30
33.3
kHz
SSC clock input frequency deviation
0
-0.50
kHz
Operating free-air temperature, TA
Commericial
0
85
C
Operating free-air temperature, TA
Industrial
-40
85
C
NOTES:
4. Unused inputs must be held high or low to prevent them from floating.
5. All devices on the serial interface bus, with input levels related to VDDI, must have one common supply line to which the pullup resistor
is connected to.
6. DC input signal voltage specifies the allowable dc execution of differential input.
7. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
CDCV850, CDCV850I
2.5 V PHASE LOCK LOOP CLOCK DRIVER
WITH 2 LINE SERIAL INTERFACE
SCAS647B - OCTOBER 2000 - REVISED DECEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input voltage
All inputs
VDDQ = 2.3 V,
II = 18 mA
1.2
V
VOH
High-level output voltage
VDDQ = min to max, IOH = 1 mA
VDDQ 0.1
V
VOH
High-level output voltage
VDDQ = 2.3 V,
IOH = 12 mA
1.7
V
Low-level output
VDDQ = min to max, IOL = 1 mA
0.1
VOL
Low-level output
voltage
VDDQ = 2.3 V,
IOL = 12 mA
0.6
V
VOL
voltage
SDATA
VDDI = 3.0 V,
IOL = 3 mA
0.4
V
IOH
High-level output current
VDDQ = 2.3 V,
VO = 1 V
18
32
mA
IOL
Low-level output current
VDDQ = 2.3 V,
VO = 1.2 V
26
35
mA
VO
Output voltage swing
For load condition see Figure 3
1.1
VDDQ 0.4
V
VOX
Output differential cross
voltage
VDDQ/2 - 0.2 VDDQ/2
VDDQ/2 + 0.2
V
II
Input current
SDATA,
SCLK
VDDQ = 3.6 V,
VI = 0 V to 3.6 V
+10/-50
A
II
Input current
CLK, FBIN
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
10
A
IOZ
High-impedance-state output
current
VDDQ = 2.7 V,
VO = VDDQ or GND
10
A
IDDPD
Power-down current on VDDQ
+ AVDD
CLK at 0 MHz;
of IDD and AIDD
150
250
A
IDDPD
Power down current on VDDI
CLK at 0 MHz; VDDQ = 3.6 V
3
20
A
IDD
Dynamic current on VDDQ
VDDQ = 2.7 V,
fO = 100 MHz
All differential output pairs are terminated
with 120
/ CL = 4 pF
205
230
mA
AI(DD)
Supply current on AVDD
AVDD = 2.7 V,
fO = 100 MHz
4
6
mA
IDDI
Supply current on VDDI
VDDI = 3.6 V
SCLK and
SDATA = 3.6 V
1
2
mA
CI
Input capacitance
VDDQ = 2.5 V
VI = VDDQ or GND
2
2.5
3
pF
CO
Output capacitance
VDDQ = 2.5 V
VO = VDDQ or GND
2.5
3
3.5
pF
All typical values are at respective nominal VDDQ.
The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-
resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
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