CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A AUGUST 2000 REVISED OCTOBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D
Spread Spectrum Clock Compatible
D
Operating Frequency: 60 to 200 MHz
D
Low Jitter (cyccyc):
75 ps
D
Distributes One Differential Clock Input to
Ten Differential Outputs
D
Three-State Outputs When the Input
Differential Clocks Are <20 MHz
D
Operates From Dual 2.5-V Supplies
D
48-Pin TSSOP Package
D
Consumes < 200-
A Quiescent Current
D
External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
description
The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT, FBOUT). The clock outputs are
controlled by the clock inputs (CLK, CLK), the
feedback clocks (FBIN, FBIN), and the analog
power input (AV
DD
). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.
When AV
DD
is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0
C
to 85
C.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y0
Y0
V
DDQ
Y1
Y1
GND
GND
Y2
Y2
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
Y3
Y3
V
DDQ
Y4
Y4
GND
GND
Y5
Y5
V
DDQ
Y6
Y6
GND
GND
Y7
Y7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y8
Y8
V
DDQ
Y9
Y9
GND
DGG PACKAGE
(TOP VIEW)
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A AUGUST 2000 REVISED OCTOBER 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
PWRDWN
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
GND
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz
<20 MHz
Z
Z
Z
Z
Off
functional block diagram
30
Y8
29
40
Y7
39
43
Y6
44
47
Y5
46
23
Y4
22
19
Y3
20
9
Y2
10
6
Y1
5
Y0
3
2
26
Y9
27
33
FBOUT
32
Powerdown
and Test
Logic
16
37
13
36
14
35
PLL
PWRDWN
AVDD
CK
CK
FBIN
FBIN
FBOUT
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A AUGUST 2000 REVISED OCTOBER 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
17
Ground for 2.5
-
V analog supply
AVDD
16
2.5
-
V Analog supply
CLK, CLK
13, 14
I
Differential clock input
FBIN, FBIN
35, 36
I
Feedback differential clock input
FBOUT, FBOUT
32, 33
O
Feedback differential clock output
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
PWRDWN
37
I
Output enable for Y and Y
VDDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
2.5-V Supply
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
Buffered output copies of input clock, CLK
Y[0:9]
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Buffered output copies of input clock, CLK
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
DDQ
,
AV
DD
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Notes 1 and 2)
0.5 V to V
DDQ
0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
0.5 V to V
DDQ
0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
DDQ
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current to GND or V
DDQ
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
89
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A AUGUST 2000 REVISED OCTOBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
TYP
MAX
UNIT
Supply voltage, VDDQ, AVDD
2.3
2.7
V
Low level input voltage VIL
CLK, CLK, FBIN, FBIN
VDDQ/2 0.18
V
Low level input voltage, VIL
PWRDWN
0.3
0.7
V
High level input voltage VIH
CLK, CLK, FBIN, FBIN
VDDQ/2 + 0.18
V
High level input voltage, VIH
PWRDWN
1.7
VDDQ + 0.3
V
DC input signal voltage (see Note 5)
0.3
VDDQ
V
Differential input signal voltage VID (see Note 6)
DC
CLK, FBIN
0.36
VDDQ + 0.6
V
Differential input signal voltage, VID (see Note 6)
AC
CLK, FBIN
0.7
VDDQ + 0.6
V
Output differential cross-voltage, VOX (see Note 7)
VDDQ/2 0.2 VDDQ/2
VDDQ/2 + 0.2
V
Input differential pair cross-voltage, VIX (see Note 7)
VDDQ/2 0.2
VDDQ/2 + 0.2
V
High-level output current, IOH
12
mA
Low-level output current, IOL
12
mA
Input slew rate, SR
1
4
V/ns
Operating free-air temperature, TA
0
85
C
NOTES:
4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differential input signal voltage specifies the differential voltage |VTR VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A AUGUST 2000 REVISED OCTOBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input voltage
All inputs
VDDQ = 2.3 V,
II = 18 mA
1.2
V
VOH
High level output voltage
VDDQ = min to max, IOH = 1 mA
VDDQ 0.1
V
VOH
High-level output voltage
VDDQ = 2.3 V,
IOH = 12 mA
1.7
V
VOL
Low level output voltage
VDDQ = min to max, IOL = 1 mA
0.1
V
VOL
Low-level output voltage
VDDQ = 2.3 V,
IOL = 12 mA
0.6
V
IOH
High-level output current
VDDQ = 2.3 V,
VO = 1 V
18
32
mA
IOL
Low-level output current
VDDQ = 2.3 V,
VO = 1.2 V
26
35
mA
VO
Output voltage swing
Differential outputs are terminated with
1.1
VDDQ 0.4
VOX
Output differential
cross-voltage
w
Differential outputs are terminated with
120
VDDQ/2 0.2
VDDQ/2
VDDQ/2 + 0.2
V
II
Input current
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
10
A
IOZ
High-impedance-state
output current
VDDQ = 2.7 V,
VO= VDDQ or GND
10
A
IDDPD
Power down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
of IDD and AIDD
100
200
A
IDD
Dynamic current on VDDQ
all outputs loaded
as shown in
fO = 200 MHz
275
330
mA
IDD
Dynamic current on VDDQ
as shown in
Figure 3
fO = 167 MHz
250
300
mA
AIDD
Supply current on AVDD
fO = 200 MHz
10
12
mA
AIDD
Supply current on AVDD
fO = 167 MHz
8
10
mA
CI
Input capacitance
VCC = 2.5 V
VI = VCC or GND
2
2.5
3
pF
CO
Output capacitance
VCC = 2.5 V
VO = VCC or GND
2.5
3
3.5
pF
All typical values are at respective nominal VDDQ.
The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-
resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage.
Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fCK
Operating clock frequency
60
200
MHz
fCK
Application clock frequency
60
200
MHz
Input clock duty cycle
40%
60%
Stabilization
time
W
(PLL mode)
10
s
Stabilization
time
W
(Bypass mode)
30
ns
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
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