20-Bit Latches
CY74FCT16841T
CY74FCT162841T
SCCS067 - July 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
FCT-C speed at 5.5 ns (FCT16841T Com'l)
Power-off disable outputs permits live insertion
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of
-
40C to +85C
V
CC
= 5V
10%
CY74FCT16841T Features:
64 mA sink current, 32 mA source current
Typical V
OLP
(ground bounce) <1.0V at V
CC
= 5V,
T
A
= 25C
CY74FCT162841T Features:
Balanced 24 mA output drivers
Reduced system switching noise
Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25C
Functional Description
The CY74FCT16841T and CY74FCT162841T are 20-bit
D-type latches designed for use in bus applications requiring
high speed and low power. These devices can be used as two
independent 10-bit latches, or as a single 10-bit latch, or as a
single 20-bit latch by connecting the Output Enable (OE) and
Latch (LE) inputs. Flow-through pinout and small shrink
packaging aid in simplifying board layout. The output buffers
are designed with a power-off disable feature to allow live
insertion of boards.
The
CY74FCT16841T
is
ideally
suited
for
driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162841T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162841T is ideal for driving transmission lines.
C
GND
1
D
1
Pin Configuration
TO 9 OTHER CHANNELS
C
2
D
1
2
Q
1
2
LE
2
OE
D
1
Q
7
1
OE
SSOP/TSSOP
Top View
1
Q
1
1
LE
1
OE
1
Q
1
1
Q
2
1
Q
3
1
Q
4
1
D
1
1
D
2
1
D
3
1
D
4
1
LE
GND
GND
V
CC
1
Q
5
1
Q
6
1
D
5
1
D
6
V
CC
GND
2
D
1
GND
GND
V
CC
V
CC
GND
D
1
Q
8
1
Q
10
2
Q
1
1
Q
9
2
Q
2
2
Q
3
2
Q
4
2
Q
5
2
Q
6
2
Q
7
2
Q
8
2
Q
9
2
Q
10
2
OE
1
D
7
GND
1
D
8
1
D
9
1
D
10
2
D
2
2
D
3
2
D
4
2
D
5
2
D
6
2
D
7
2
D
8
2
D
9
2
D
10
2
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FCT16841-1
FCT16841-2
FCT16841-3
TO 9 OTHER CHANNELS
Logic Block Diagrams
CY74FCT16841T
CY74FCT162841T
2
Maximum Ratings
[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature
......................................-
55
C to +125
C
Ambient Temperature with
Power Applied
..................................................-
55
C to +125
C
DC Input Voltage
.................................................-
0.5V to +7.0V
DC Output Voltage
..............................................-
0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)
...........................-
60 to +120 mA
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Pin Description
Name
Description
D
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
O
Three-State Outputs
Function Table
[1]
Inputs
Outputs
D
LE
OE
Q
H
H
L
H
L
H
L
L
X
L
L
Q
[2]
X
X
H
Z
Operating Range
Range
Ambient
Temperature
V
CC
Industrial
-
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
[5]
Max.
Unit
V
IH
Input HIGH Voltage
Logic HIGH Level
2.0
V
V
IL
Input LOW Voltage
Logic LOW Level
0.8
V
V
H
Input Hysteresis
[6]
100
mV
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=
-
18 mA
-
0.7
-
1.2
V
I
IH
Input HIGH Current
V
CC
=Max., V
I
=V
CC
1
A
I
IL
Input LOW Current
V
CC
=Max., V
I
=GND
1
A
I
OZH
High Impedance Output
Current (Three-State Output pins)
V
CC
=Max., V
OUT
=2.7V
1
A
I
OZL
High Impedance Output
Current (Three-State Output pins)
V
CC
=Max., V
OUT
=0.5V
1
A
I
OS
Short Circuit Current
[7]
V
CC
=Max., V
OUT
=GND
-
80
-
140
-
200
mA
I
O
Output Drive Current
[7]
V
CC
=Max., V
OUT
=2.5V
-
50
-
180
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
4.5V
[8]
1
A
Notes:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. Z = HIGH Impedance.
2.
Output level before LE HIGH-to-LOW Transition.
3.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
5.
Typical values are at V
CC
= 5.0V, T
A
= +25C ambient.
6.
This parameter is specified but not tested.
7.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
8.
Tested at +25C.
CY74FCT16841T
CY74FCT162841T
3
Output Drive Characteristics for CY74FCT16841T
Parameter
Description
Test Conditions
Min.
Typ.
[5]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=
-
3 mA
2.5
3.5
V
V
CC
=Min., I
OH
=
-
15 mA
2.4
3.5
V
CC
=Min., I
OH
=
-
32 mA
2.0
3.0
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
0.2
0.55
V
Output Drive Characteristics for CY74FCT162841T
Parameter
Description
Test Conditions
Min.
Typ.
[5]
Max.
Unit
I
ODL
Output LOW Current
[7]
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
60
115
150
mA
I
ODH
Output HIGH Current
[7]
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
-
60
-
115
-
150
mA
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=
-
24 mA
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=24 mA
0.3
0.55
V
Capacitance
[6]
(T
A
=+25C, f = 1.0 MHz)
Symbol
Description
Conditions
Typ.
[5]
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6.0
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8.0
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Min.
Typ.
[5]
Max.
Unit
I
CC
Quiescent Power Supply
Current
V
CC
=Max.
V
IN
<0.2V
V
IN
>V
CC
-0.2V
--
5
500
A
I
CC
Quiescent Power Supply
Current (TTL inputs HIGH)
V
CC
=Max.,
V
IN
=3.4V
[9]
--
0.5
1.5
mA
I
CCD
Dynamic Power Supply
Current
[10]
V
CC
=Max., One Input
Toggling, 50% Duty
Cycle, Outputs Open,
OE=GND
V
IN
=V
CC
or
V
IN
=GND
--
60
100
A/MHz
I
C
Total Power Supply Current
[11]
V
CC
=Max., f
1
=10 MHz,
50% Duty Cycle,
Outputs Open, One Bit
Toggling, OE=GND
LE = V
CC
V
IN
=V
CC
or
V
IN
=GND
--
0.6
1.5
mA
V
IN
=3.4V or
V
IN
=GND
--
0.9
2.3
V
CC
=Max., f
1
=2.5 MHz,
50% Duty Cycle, Outputs
Open, Twenty Bits
Toggling, OE=GND
LE = V
CC
V
IN
=V
CC
or
V
IN
=GND
--
3.0
5.5
[12]
V
IN
=3.4V or
V
IN
=GND
--
8.0
20.5
[12]
Notes:
9.
Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
11. I
C
=
I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
=
I
CC
+
I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
=
Quiescent Current with CMOS input levels
I
CC
=
Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
=
Duty Cycle for TTL inputs HIGH
N
T
=
Number of TTL inputs at D
H
I
CCD
=
Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
=
Clock frequency for registered devices, otherwise zero
f
1
=
Input signal frequency
N
1
=
Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
CY74FCT16841T
CY74FCT162841T
4
Switching Characteristics
Over the Operating Range
[13]
74FCT16841AT
74FCT16841CT
74FCT162841CT
Fig.
No.
[15]
Parameter
Description
Condition
[14]
Min.
Max.
Min.
Max.
Unit
t
PLH
t
PHL
Propagation Delay
D to Q
(LE=HIGH)
C
L
=50 pF
R
L
=500
1.5
9.0
1.5
5.5
ns
1, 5
C
L
=300 pF
[16]
R
L
=500
1.5
13.0
1.5
13.0
t
PLH
t
PHL
Propagation Delay
LE to Q
C
L
=50 pF
R
L
=500
1.5
12.0
1.5
6.4
ns
1, 5
C
L
=300 pF
[16]
R
L
=500
1.5
16.0
1.5
15.0
t
PHZ
t
PZL
Output Enable Time
OE to Q
C
L
=50 pF
R
L
=500
1.5
11.5
1.5
6.5
ns
1, 7, 8
C
L
=300 pF
[16]
R
L
=500
1.5
23.0
1.5
12.0
t
PHZ
t
PLZ
Output Disable Time
OE to Q
C
L
=5 pF
[16]
R
L
=500
1.5
7.0
1.5
5.7
ns
1, 7, 8
C
L
=50 pF
R
L
=500
1.5
8.0
1.5
6.0
t
SU
Set-Up Time
HIGH or LOW, D to LE
C
L
=50 pF
R
L
=500
2.5
--
2.0
--
ns
9
t
H
Hold Time
HIGH or LOW, D to LE
2.5
--
1.5
--
ns
9
t
W
LE Pulse Width HIGH
4.0
[17]
--
4.0
[17]
--
ns
5
t
SK(O)
Output Skew
[18]
--
0.5
--
0.5
ns
--
Notes:
13. Minimum limits are specified but not tested on Propagation Delays.
14. See test circuit and waveform.
15. See "Parameter Measurement Information" in the General Information section.
16. These conditions are specified but not tested.
17. These limits are specified but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
Ordering Information for CY74FCT16841T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
5.5
CY74FCT16841CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
6.5
CY74FCT16841ATPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Industrial
Ordering Information CY74FCT162841T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
5.5
74FCT162841CTPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
CY74FCT162841CTPVC
O56
56-Lead (300-Mil) SSOP
74FCT162841CTPVCT
O56
56-Lead (300-Mil) SSOP
CY74FCT16841T
CY74FCT162841T
5
Package Diagrams
56-Lead Shrunk Small Outline PackageO56
56-Lead Thin Shrunk Small Outline Package Z56
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Copyright
2000, Texas Instruments Incorporated
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