DAC900
DAC900
10-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
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SINGLE +5V OR +3V OPERATION
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HIGH SFDR: 5MHz Output at 100MSPS: 68dBc
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LOW GLITCH: 3pV-s
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LOW POWER: 170mW at +5V
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INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
APPLICATIONS
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COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
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WAVEFORM GENERATION
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
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MEDICAL/ULTRASOUND
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HIGH-SPEED INSTRUMENTATION AND CON-
TROL
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VIDEO, DIGITAL TV
DESCRIPTION
The DAC900 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 10-bit resolution option within the SpeedPlus family of
high-performance converters. Featuring pin compatibility among
family members, the DAC908, DAC902, and DAC904 provide a
component selection option to an 8-, 12-, and 14-bit resolution,
respectively. All models within this family of DACs support update
rates in excess of 165MSPS with excellent dynamic performance,
and are especially suited to fulfill the demands of a variety of
applications.
The advanced segmentation architecture of the DAC900 is opti-
mized to provide a high Spurious-Free Dynamic Range (SFDR) for
single-tone, as well as for multi-tone signals--essential when used
for the transmit signal path of communication systems.
The DAC900 has a high impedance (200k
) current output with a
nominal range of 20mA and an output compliance of up to 1.25V.
The differential outputs allow for both a differential or single-
ended analog signal interface. The close matching of the current
outputs ensures superior dynamic performance in the differential
configuration, which can be implemented with a transformer.
Utilizing a small geometry CMOS process, the monolithic DAC900
can be operated on a wide, single-supply range of +2.7V to +5.5V.
Its low power consumption allows for use in portable and battery-
operated systems. Further optimization can be realized by lowering
the output current with the adjustable full-scale option.
For noncontinuous operation of the DAC900, a power-down mode
results in only 45mW of standby power.
The DAC900 comes with an integrated 1.24V bandgap reference
and edge-triggered input latches, offering a complete converter
solution. Both +3V and +5V CMOS logic families can be inter-
faced to the DAC900.
The reference structure of the DAC900 allows for additional
flexibility by utilizing the on-chip reference, or applying an exter-
nal reference. The full-scale output current can be adjusted over a
span of 2mA to 20mA, with one external resistor, while maintain-
ing the specified dynamic performance.
The DAC900 is available in SO-28 and TSSOP-28 packages.
Current
Sources
LSB
Switches
Segmented
Switches
+1.24V Ref.
Latches
10-Bit Data Input
D9...D0
DAC900
FSA
BW
+V
D
+V
A
AGND
CLK
DGND
REF
IN
INT/EXT
I
OUT
I
OUT
BYP
PD
DAC900
SBAS093B MAY 2002
www.ti.com
PRODUCTION DATA information is current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TM
DAC900
2
SBAS093B
ELECTRICAL CHARACTERISTICS
At T
A
= full specified temperature range, +V
A
= +5V, +V
D
= +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
10
Bits
OUTPUT UPDATE RATE
2.7V to 3.3V
125
165
MSPS
Output Update Rate (f
CLOCK
)
4.5V to 5.5V
165
200
MSPS
Full Specified Temperature Range, Operating
Ambient, T
A
40
+85
C
STATIC ACCURACY
(1)
T
A
= +25C
Differential Nonlinearity (DNL)
f
CLOCK
= 25MSPS, f
OUT
= 1.0MHz
0.5
0.3
+0.5
LSB
Integral Nonlinearity (INL)
1.0
0.5
+1.0
LSB
DYNAMIC PERFORMANCE
T
A
= +25C
Spurious-Free Dynamic Range (SFDR)
To Nyquist
f
OUT
= 1.0MHz, f
CLOCK
= 25MSPS
70
76
dBc
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
75
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 50MSPS
68
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
68
dBc
f
OUT
= 20.2MHz, f
CLOCK
= 100MSPS
62
dBc
f
OUT
= 25.3MHz, f
CLOCK
= 125MSPS
62
dBc
f
OUT
= 41.5MHz, f
CLOCK
= 125MSPS
53
dBc
f
OUT
= 27.4MHz, f
CLOCK
= 165MSPS
59
dBc
f
OUT
= 54.8MHz, f
CLOCK
= 165MSPS
53
dBc
Spurious-Free Dynamic Range within a Window
f
OUT
= 5.04MHz, f
CLOCK
= 50MSPS
2MHz Span
78
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
4MHz Span
78
dBc
Total Harmonic Distortion (THD)
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
74
dBc
f
OUT
= 2.1MHz, f
CLOCK
= 125MSPS
73
dBc
Two Tone
f
OUT1
= 13.5MHz, f
OUT2
= 14.5MHz, f
CLOCK
= 100MSPS
60
dBc
Output Settling Time
(2)
to 0.1%
30
ns
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
DAC900U
SO-28
217
40C to +85C
DAC900U
DAC900U
Rails
"
"
"
"
"
DAC900U/1K
Tape and Reel
DAC900E
TSSOP-28
360
40C to +85C
DAC900E
DAC900E
Rails
"
"
"
"
"
DAC900E/2K5
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "DAC900E/2K5" will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
DEMO BOARD
PRODUCT
ORDERING NUMBER
COMMENT
DAC900U
DEM-DAC90xU
Populated evaluation board without DAC. Order sample of desired DAC90x model separately.
DAC900E
DEM-DAC900E
Populated evaluation board including the DAC900E.
DEMO BOARD ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
+V
A
to AGND ........................................................................ 0.3V to +6V
+V
D
to DGND ........................................................................ 0.3V to +6V
AGND
to DGND ................................................................. 0.3V to +0.3V
+V
A
to +V
D
............................................................................... 6V to +6V
CLK, PD to DGND ..................................................... 0.3V to V
D
+ 0.3V
D0-D9 to DGND ......................................................... 0.3V to V
D
+ 0.3V
I
OUT
, I
OUT
to AGND ........................................................ 1V to V
A
+ 0.3V
BW, BYP to AGND ..................................................... 0.3V to V
A
+ 0.3V
REF
IN
, FSA to AGND ................................................. 0.3V to V
A
+ 0.3V
INT/EXT to AGND ...................................................... 0.3V to V
A
+ 0.3V
Junction Temperature .................................................................... +150C
Case Temperature ......................................................................... +100C
Storage Temperature .................................................................... +125C
DAC900
3
SBAS093B
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= +25C, +V
A
= +5V, +V
D
= +5V, differential transformer coupled output, 50
doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (Cont.)
Output Rise Time
(2)
10% to 90%
2
ns
Output Fall Time
(2)
10% to 90%
2
ns
Glitch Impulse
3
pV-s
DC-ACCURACY
Full-Scale Output Range
(3)
(FSR)
All Bits High, I
OUT
2.0
20.0
mA
Output Compliance Range
1.0
+1.25
V
Gain Error
With Internal Reference
10
1
+10
%FSR
Gain Error
With External Reference
10
2
+10
%FSR
Gain Drift
With Internal Reference
120
ppmFSR/C
Offset Error
With Internal Reference
0.025
+0.025
%FSR
Offset Drift
With Internal Reference
0.1
ppmFSR/C
Power-Supply Rejection, +V
A
0.2
+0.2
%FSR/V
Power-Supply Rejection, +V
D
0.025
+0.025
%FSR/V
Output Noise
I
OUT
= 20mA, R
LOAD
= 50
50
pA/
Hz
Output Resistance
200
k
Output Capacitance
I
OUT
, I
OUT
to Ground
12
pF
REFERENCE
Reference Voltage
+1.24
V
Reference Tolerance
10
%
Reference Voltage Drift
50
ppmFSR/C
Reference Output Current
10
A
Reference Input Resistance
1
M
Reference Input Compliance Range
0.1
1.25
V
Reference Small-Signal Bandwidth
(4)
1.3
MHz
DIGITAL INPUTS
Logic Coding
Straight Binary
Latch Command
Rising Edge of Clock
Logic High Voltage, V
IH
+V
D
= +5V
3.5
5
V
Logic Low Voltage, V
IL
+V
D
= +5V
0
1.2
V
Logic High Voltage, V
IH
+V
D
= +3V
2
3
V
Logic Low Voltage, V
IL
+V
D
= +3V
0
0.8
V
Logic High Current
,
I
IH
(5)
+V
D
= +5V
20
A
Logic Low Current, I
IL
+V
D
= +5V
20
A
Input Capacitance
5
pF
POWER SUPPLY
Supply Voltages
+V
A
+2.7
+5
+5.5
V
+V
D
+2.7
+5
+5.5
V
Supply Current
(6)
I
VA
24
30
mA
I
VA
, Power-Down Mode
1.1
2
mA
I
VD
8
15
mA
Power Dissipation
+5V, I
OUT
= 20mA
170
230
mW
+3V, I
OUT
= 2mA
50
mW
Power Dissipation, Power-Down Mode
45
mW
Thermal Resistance,
JA
SO-28
75
C/W
TSSOP-28
50
C/W
NOTES: (1) At output I
OUT
, while driving a virtual ground. (2) Measured single-ended into 50
Load. (3) Nominal full-scale output current is 32x I
REF
; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45A for the PD pin, which has an
internal pull-down resistor. (6) Measured at f
CLOCK
= 50MSPS and f
OUT
= 1.0MHz.
DAC900
4
SBAS093B
Current
Sources
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref.
Latches
10-Bit Data Input
D9.......D0
DAC900
FSA
BW
+V
D
+V
A
R
SET
AGND
CLK
DGND
REF
IN
0.1
F
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
50
50
20pF
1:1
0.1
F
0.1
F
+5V
+5V
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
NC
NC
NC
NC
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC900
PIN
DESIGNATOR
DESCRIPTION
1
Bit 1
Data Bit 1 (D9), MSB
2
Bit 2
Data Bit 2 (D8)
3
Bit 3
Data Bit 3 (D7)
4
Bit 4
Data Bit 4 (D6)
5
Bit 5
Data Bit 5 (D5)
6
Bit 6
Data Bit 6 (D4)
7
Bit 7
Data Bit 7 (D3)
8
Bit 8
Data Bit 8 (D2)
9
Bit 9
Data Bit 9 (D1)
10
Bit 10
Data Bit 10 (D0), LSB
11
NC
No Connection
12
NC
No Connection
13
NC
No Connection
14
NC
No Connection
15
PD
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
16
INT/EXT
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
17
REF
IN
Reference Input/Ouput. See Applications
section for further details.
18
FSA
Full-Scale Output Adjust
19
BW
Bandwidth/Noise Reduction Pin:
Bypass with 0.1F to +V
A
for Optimum
Performance.
20
AGND
Analog Ground
21
I
OUT
Complementary DAC Current Output
22
I
OUT
DAC Current Output
23
BYP
Bypass Node: Use 0.1F to AGND
24
+V
A
Analog Supply Voltage, 2.7V to 5.5V
25
NC
No Connection
26
DGND
Digital Ground
27
+V
D
Digital Supply Voltage, 2.7V to 5.5V
28
CLK
Clock Input
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SO, TSSOP
TYPICAL CONNECTION CIRCUIT
DAC900
5
SBAS093B
TIMING DIAGRAM
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
Clock Pulse HIGH Time
3
ns
t
2
Clock Pulse LOW Time
3
ns
t
S
Data Setup Time
1.5
ns
t
H
Data Hold Time
1.0
ns
t
PD
Propagation Delay Time
1
ns
t
SET
Output Settling Time to 0.1%
30
ns
t2
t1
tS
tH
tSET
tPD
CLOCK
D13 D0
Iout or
Iout
Data Changes
Stable Valid Data
Data Changes
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