DAC902
DAC902
12-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q
q
q
q
q
SINGLE +5V OR +3V OPERATION
q
q
q
q
q
HIGH SFDR: 5MHz Output at 100MSPS: 67dBc
q
q
q
q
q
LOW GLITCH: 3pV-s
q
q
q
q
q
LOW POWER: 170mW at +5V
q
q
q
q
q
INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
APPLICATIONS
q
q
q
q
q
COMMUNICATION TRANSMIT CHANNELS:
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
q
q
q
q
q
WAVEFORM GENERATION:
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
q
q
q
q
q
MEDICAL/ULTRASOUND
q
q
q
q
q
HIGH-SPEED INSTRUMENTATION AND CON-
TROL
q
q
q
q
q
VIDEO, DIGITAL TV
DESCRIPTION
The DAC902 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 12-bit resolution option within the SpeedPlus Family of
high-performance converters. Featuring pin compatibility among
family members, the DAC908, DAC900, and DAC904 provide a
component selection option to an 8-, 10-, and 14-bit resolution,
respectively. All models within this family of DACs support update
rates in excess of 165MSPS with excellent dynamic performance,
and are especially suited to fulfill the demands of a variety of
applications.
The advanced segmentation architecture of the DAC902 is opti-
mized to provide a high Spurious-Free Dynamic Range (SFDR) for
single-tone, as well as for multi-tone signals--essential when used
for the transmit signal path of communication systems.
The DAC902 has a high impedance (200k
) current output with a
nominal range of 20mA and an output compliance of up to 1.25V.
The differential outputs allow for both a differential or single-
ended analog signal interface. The close matching of the current
outputs ensures superior dynamic performance in the differential
configuration, which can be implemented with a transformer.
Utilizing a small geometry CMOS process, the monolithic DAC902
can be operated on a wide, single-supply range of +2.7V to +5.5V.
Its low power consumption allows for use in portable and battery-
operated systems. Further optimization can be realized by lowering
the output current with the adjustable full-scale option.
For noncontinuous operation of the DAC902, a power-down mode
results in only 45mW of standby power.
The DAC902 comes with an integrated 1.24V bandgap reference
and edge-triggered input latches, offering a complete converter
solution. Both +3V and +5V CMOS logic families can be inter-
faced to the DAC902.
The reference structure of the DAC902 allows for additional
flexibility by utilizing the on-chip reference, or applying an exter-
nal reference. The full-scale output current can be adjusted over a
span of 2mA to 20mA, with one external resistor, while maintain-
ing the specified dynamic performance.
The DAC902 is available in the SO-28 and TSSOP-28 packages.
Current
Sources
LSB
Switches
Segmented
Switches
+1.24V Ref.
Latches
12-Bit Data Input
D11...D0
DAC902
FSA
BW
+V
D
+V
A
AGND
CLK
DGND
REF
IN
INT/EXT
I
OUT
I
OUT
BYP
PD
DAC902
SBAS094B - MAY 2002
www.ti.com
PRODUCTION DATA information is current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TM
DAC902
2
SBAS094B
ELECTRICAL CHARACTERISTICS
At T
A
= full specified temperature range, +V
A
= +5V, +V
D
= +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified.
DAC902U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
OUTPUT UPDATE RATE
2.7V to 3.3V
125
165
MSPS
Output Update Rate (f
CLOCK
)
4.5V to 5.5V
165
200
MSPS
Full Specified Temperature Range, Operating
Ambient, T
A
40
+85
C
STATIC ACCURACY
(1)
T
A
= +25C
Differential Nonlinearity (DNL)
f
CLOCK
= 25MSPS, f
OUT
= 1.0MHz
1.75
0.5
+1.75
LSB
Integral Nonlinearity (INL)
2.5
1.0
+2.5
LSB
DYNAMIC PERFORMANCE
T
A
= +25C
Spurious-Free Dynamic Range (SFDR)
To Nyquist
f
OUT
= 1MHz, f
CLOCK
= 25MSPS
71
77
dBc
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
75
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 50MSPS
68
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
67
dBc
f
OUT
= 20.2MHz, f
CLOCK
= 100MSPS
61
dBc
f
OUT
= 25.3MHz, f
CLOCK
= 125MSPS
61
dBc
f
OUT
= 41.5MHz, f
CLOCK
= 125MSPS
57
dBc
f
OUT
= 27.4MHz, f
CLOCK
= 165MSPS
60
dBc
f
OUT
= 54.8MHz, f
CLOCK
= 165MSPS
53
dBc
Spurious-Free Dynamic Range within a Window
f
OUT
= 5.04MHz, f
CLOCK
= 50MSPS
2MHz Span
80
dBc
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
4MHz Span
80
dBc
Total Harmonic Distortion (THD)
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
74
dBc
f
OUT
= 2.1MHz, f
CLOCK
= 125MSPS
75
dBc
Two Tone
f
OUT1
= 13.5MHz, f
OUT2
= 14.5MHz, f
CLOCK
= 100MSPS
64
dBc
ABSOLUTE MAXIMUM RATINGS
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
DAC902U
SO-28
217
40C to +85C
DAC902U
DAC902U
Rails
"
"
"
"
"
DAC902U/1K
Tape and Reel
DAC902E
TSSOP-28
360
40C to +85C
DAC902E
DAC902E
Rails
"
"
"
"
"
DAC902E/2K5
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "DAC902E/2K5" will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
+V
A
to AGND ........................................................................ 0.3V to +6V
+V
D
to DGND ........................................................................ 0.3V to +6V
AGND
to DGND ................................................................. 0.3V to +0.3V
+V
A
to +V
D .............................................................................................................
6V to +6V
CLK, PD to DGND ..................................................... 0.3V to V
D
+ 0.3V
D0-D11 to DGND ....................................................... 0.3V to V
D
+ 0.3V
I
OUT
, I
OUT
to AGND ........................................................ 1V to V
A
+ 0.3V
BW, BYP to AGND ..................................................... 0.3V to V
A
+ 0.3V
REF
IN
, FSA to AGND ................................................. 0.3V to V
A
+ 0.3V
INT/EXT to AGND ...................................................... 0.3V to V
A
+ 0.3V
Junction Temperature .................................................................... +150C
Case Temperature ......................................................................... +100C
Storage Temperature .................................................................... +125C
DEMO BOARD
PRODUCT
ORDERING NUMBER
COMMENT
DAC902U
DEM-DAC90xU
Populated evaluation board without the DAC. Order sample of desired DAC90x model separately.
DAC902E
DEM-DAC902E
Populated evaluation board including the DAC902E.
DEMO BOARD ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
DAC902
3
SBAS094B
DAC902U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= full specified temperature range, +V
A
= +5V, +V
D
= +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified.
DYNAMIC PERFORMANCE (Cont.)
Output Settling Time
(2)
to 0.1%
30
ns
Output Rise Time
(2)
10% to 90%
2
ns
Output Fall Time
(2)
10% to 90%
2
ns
Glitch Impulse
3
pV-s
DC-ACCURACY
Full-Scale Output Range
(3)
(FSR)
All Bits High, I
OUT
2.0
20.0
mA
Output Compliance Range
1.0
+1.25
V
Gain Error
With Internal Reference
10
1
+10
%FSR
Gain Error
With External Reference
10
2
+10
%FSR
Gain Drift
With Internal Reference
120
ppmFSR/C
Offset Error
With Internal Reference
0.025
+0.025
%FSR
Offset Drift
With Internal Reference
0.1
ppmFSR/C
Power-Supply Rejection, +V
A
0.2
+0.2
%FSR/V
Power-Supply Rejection, +V
D
0.025
+0.025
%FSR/V
Output Noise
I
OUT
= 20mA, R
LOAD
= 50
50
pA/
Hz
Output Resistance
200
k
Output Capacitance
I
OUT
, I
OUT
to Ground
12
pF
REFERENCE
Reference Voltage
+1.24
V
Reference Tolerance
5
%
Reference Voltage Drift
50
ppmFSR/C
Reference Output Current
10
A
Reference Input Resistance
1
M
Reference Input Compliance Range
0.1
1.25
V
Reference Small-Signal Bandwidth
(4)
1.3
MHz
DIGITAL INPUTS
Logic Coding
Straight Binary
Latch Command
Rising Edge of Clock
Logic High Voltage, V
IH
+V
D
= +5V
3.5
5
V
Logic Low Voltage, V
IL
+V
D
= +5V
0
1.2
V
Logic High Voltage, V
IH
+V
D
= +3V
2
3
V
Logic Low Voltage, V
IL
+V
D
= +3V
0
0.8
V
Logic High Current
,
I
IH
(5)
+V
D
= +5V
20
A
Logic Low Current, I
IL
+V
D
= +5V
20
A
Input Capacitance
5
pF
POWER SUPPLY
Supply Voltages
+V
A
+2.7
+5
+5.5
V
+V
D
+2.7
+5
+5.5
V
Supply Current
(6)
I
VA
24
30
mA
I
VA
, Power-Down Mode
1.1
2
mA
I
VD
8
15
mA
Power Dissipation
+5V, I
OUT
= 20mA
170
230
mW
+3V, I
OUT
= 2mA
50
mW
Power Dissipation, Power-Down Mode
45
mW
Thermal Resistance,
JA
SO-28
75
C/W
TSSOP-28
50
C/W
NOTES: (1) At output I
OUT
, while driving a virtual ground. (2) Measured single-ended into 50
Load. (3) Nominal full-scale output current is 32 I
REF
; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45A for the PD pin, which has an
internal pull-down resistor. (6) Measured at f
CLOCK
= 50MSPS and f
OUT
= 1.0MHz.
DAC902
4
SBAS094B
PIN
DESIGNATOR
DESCRIPTION
1
Bit 1
Data Bit 1 (D11), MSB
2
Bit 2
Data Bit 2 (D10)
3
Bit 3
Data Bit 3 (D9)
4
Bit 4
Data Bit 4 (D8)
5
Bit 5
Data Bit 5 (D7)
6
Bit 6
Data Bit 6 (D6)
7
Bit 7
Data Bit 7 (D5)
8
Bit 8
Data Bit 8 (D4)
9
Bit 9
Data Bit 9 (D3)
10
Bit 10
Data Bit 10 (D2)
11
Bit 11
Data Bit 11 (D1)
12
Bit 12
Data Bit 12 (D0), LSB
13
NC
No Connection
14
NC
No Connection
15
PD
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
16
INT/EXT
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
17
REF
IN
Reference Input/Ouput. See Applica-
tions section for further details.
18
FSA
Full-Scale Output Adjust
19
BW
Bandwidth/Noise Reduction Pin:
Bypass with 0.1F to +V
A
for Optimum
Performance.
20
AGND
Analog Ground
21
I
OUT
Complementary DAC Current Output
22
I
OUT
DAC Current Output
23
BYP
Bypass Node: Use 0.1F to AGND
24
+V
A
Analog Supply Voltage, 2.7V to 5.5V
25
NC
No Connection
26
DGND
Digital Ground
27
+V
D
Digital Supply Voltage, 2.7V to 5.5V
28
CLK
Clock Input
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SO, TSSOP
TYPICAL CONNECTION CIRCUIT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
NC
NC
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC902
Current
Sources
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref.
Latches
12-Bit Data Input
D11.......D0
DAC902
FSA
BW
+V
D
+V
A
R
SET
AGND
CLK
DGND
REF
IN
0.1
F
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
50
50
20pF
1:1
0.1
F
0.1
F
+5V
+5V
DAC902
5
SBAS094B
TIMING DIAGRAM
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
Clock Pulse HIGH Time
3.0
ns
t
2
Clock Pulse LOW Time
3.0
ns
t
S
Data Setup Time
1.0
ns
t
H
Data Hold Time
1.5
ns
t
PD
Propagation Delay Time
1
ns
t
SET
Output Settling Time to 0.1%
30.0
ns
t2
t1
tS
tH
tSET
tPD
CLOCK
D13 D0
Iout or
Iout
Data Changes
Stable Valid Data
Data Changes
DAC902
6
SBAS094B
TYPICAL CHARACTERISTICS: V
D
= V
A
= +5V
At T
A
= +25C, differential transformer coupled output, 50 doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
SFDR vs f
OUT
AT 25MSPS
Frequency (MHz)
SFDR (dBc)
90
85
80
75
70
65
60
2.0
4.0
6.0
8.0
10.0
12.0
0
0dBFS
6dBFS
SFDR vs f
OUT
AT 50MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
5.0
10.0
15.0
20.0
25.0
0
6dBFS
0dBFS
SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
40.0
50.0
0
0dBFS
6dBFS
SFDR vs f
OUT
AT 125MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
50.0
40.0
60.0
0
0dBFS
6dBFS
DAC Code
TYPICAL DNL
Error (LSBs)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
0
500
1000
1500
2000
2500
3000
3500
4000
4096
DAC Code
TYPICAL INL
Error (LSBs)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
0
500
1000
1500
2000
2500
3000
3500
4000
4096
DAC902
7
SBAS094B
TYPICAL CHARACTERISTICS: V
D
= V
A
= +5V
(Cont.)
At T
A
= +25C, differential transformer coupled output, 50 doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
Temperature (
C)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
20
0
25
70
50
85
40
2.1MHz
10.1MHz
40.4MHz
X
X
X
X
X
X
X
SFDR vs I
OUTFS
and f
OUT
AT 100MSPS, 0dBFS
I
OUTFS
(mA)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
5
10
20
2
X
X
X
X
2.1MHz
20.2MHz
10.1MHz
40.4MHz
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
40.0
50.0
0
Diff (0dBFS)
I
OUT
(6dBFS)
I
OUT
(0dBFS)
Diff (6dBFS)
X
X
X
X
X
X
X
SFDR vs f
OUT
AT 200MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
20.0
10.0
30.0
40.0
50.0
70.0
60.0
90.0
80.0
0
6dBFS
0dBFS
SFDR vs f
OUT
AT 165MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
20.0
10.0
30.0
40.0
50.0
70.0
60.0
80.0
0
6dBFS
0dBFS
THD vs f
CLOCK
AT f
OUT
= 2.1MHz
f
CLOCK
(MSPS)
THD (dBc)
70
75
80
85
90
95
100
25
50
100
125
150
0
2HD
4HD
3HD
X
X
X
X
DAC902
8
SBAS094B
TYPICAL CHARACTERISTICS: V
D
= V
A
= +5V
(Cont.)
At T
A
= +25C, differential transformer coupled output, 50 doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
FOUR-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
f
CLOCK
= 50MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 66dBc
Amplitude = 0dBFS
DUAL-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
30
35
40
45
50
f
CLOCK
= 100MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
SFDR = 64dBc
Amplitude = 0dBFS
SINGLE-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
30
35
40
45
50
f
CLOCK
= 100MSPS
f
OUT
= 2.1MHz
SFDR = 74dBc
Amplitude = 0dBFS
DAC902
9
SBAS094B
TYPICAL CHARACTERISTICS: V
D
= V
A
= +3V
At T
A
= +25C, differential transformer coupled output, 50 doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
40.0
50.0
0
Diff (0dBFS)
I
OUT
(6dBFS)
I
OUT
(0dBFS)
Diff (6dBFS)
SFDR vs f
OUT
AT 165MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
20.0
10.0
30.0
40.0
50.0
70.0
60.0
80.0
0
6dBFS
0dBFS
SFDR vs f
OUT
AT 125MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
50.0
40.0
60.0
0
0dBFS
6dBFS
SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
10.0
20.0
30.0
40.0
50.0
0
6dBFS
0dBFS
SFDR vs f
OUT
AT 50MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
5.0
10.0
15.0
20.0
25.0
0
6dBFS
0dBFS
SFDR vs f
OUT
AT 25MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
2.0
4.0
6.0
8.0
10.0
12.0
0
0dBFS
6dBFS
DAC902
10
SBAS094B
TYPICAL CHARACTERISTICS: V
D
= V
A
= +3V
(Cont.)
At T
A
= +25C, differential transformer coupled output, 50 doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
FOUR-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
f
CLOCK
= 50MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 66dBc
Amplitude = 0dBFS
DUAL-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
30
35
40
45
50
f
CLOCK
= 100MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
SFDR = 68dBc
Amplitude = 0dBFS
SINGLE-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
10
20
30
40
50
60
70
80
90
100
5
10
15
20
25
30
35
40
45
50
f
CLOCK
= 100MSPS
f
OUT
= 2.1MHz
SFDR = 76dBc
Amplitude = 0dBFS
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
Temperature (
C)
SFDR (dBc)
85
80
75
70
65
60
55
50
45
20
0
25
70
50
85
40
2.1MHz
10.1MHz
40.4MHz
X
X
X
X
X
X
X
THD vs f
CLOCK
AT f
OUT
= 2.1MHz
f
CLOCK
(MSPS)
THD (dBc)
70
75
80
85
90
95
100
25
50
100
125
150
0
2HD
4HD
3HD
I
OUTFS
(mA)
SFDR (dBc)
80
75
70
65
60
55
50
45
40
5
10
20
2
X
X
X
X
SFDR vs I
OUTFS
and f
OUT
AT 100MSPS, 0dBFS
2.1MHz
20.2MHz
10.1MHz
40.4MHz
DAC902
11
SBAS094B
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC902 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a full-
scale output current of up to 20mA, as shown in Figure 1. An
internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, I
OUT
or I
OUT
. The complementary outputs
deliver a differential output signal that improves the dynamic
performance through reduction of even-order harmonics,
common-mode signals (noise), and double the peak-to-peak
output signal swing by a factor of two, compared to single-
ended operation.
The segmented architecture results in a significant reduc-
tion of the glitch energy, improves the dynamic perfor-
mance (SFDR), and DNL. The current outputs maintain a
very high output impedance of greater than 200k.
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, R
SET
. The resulting I
REF
is internally multiplied by
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value
of R
SET
.
The DAC902 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches, and the
reference circuitry.
DAC TRANSFER FUNCTION
The total output current, I
OUTFS
, of the DAC902 is the
summation of the two complementary output currents:
I
OUTFS
= I
OUT
+ I
OUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
I
OUT
= I
OUTFS
(Code/4096)
(2)
I
OUT
= I
OUTFS
(4095 Code/4096)
(3)
where `Code' is the decimal representation of the DAC data
input word. Additionally, I
OUTFS
is a function of the refer-
ence current I
REF
, which is determined by the reference
voltage and the external setting resistor, R
SET
.
I
OUTFS
= 32 I
REF
= 32 V
REF
/R
SET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
V
OUT
= I
OUT
R
LOAD
(5)
V
OUT
= I
OUT
R
LOAD
(6)
FIGURE 1. Functional Block Diagram of the DAC902.
PMOS
Current
Source
Array
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref
Latches and Switch
Decoder Logic
12-Bit Data Input
D11...D0
DAC902
Full-Scale
Adjust
Resistor
Ref
Control
Amp
Ref
Buffer
BW
+V
D
+V
A
R
SET
2k
CLK
DGND
Ref
Input
0.1
F
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
50
50
20pF
1:1
V
OUT
0.1
F
400pF
0.1
F
+3V to +5V
Analog
Bandwidth
Control
+3V to +5V
Digital
FSA
REF
IN
AGND
Analog
Ground
Digital
Ground
Power Down
(internal pull-down)
Clock
Input
NOTE: Supply bypassing not shown.
DAC902
12
SBAS094B
The value of the load resistance is limited by the output
compliance specification of the DAC902. To maintain speci-
fied linearity performance, the voltage for I
OUT
and I
OUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
(7)
ANALOG OUTPUTS
The DAC902 provides two complementary current outputs,
I
OUT
and I
OUT
. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200k
|| 12pF for I
OUT
and I
OUT
results from the parallel combination of the differ-
ential switches, along with the current sources and associ-
ated parasitic capacitances.
I
OUT
and I
OUT
. Furthermore, using the differential output
configuration in combination with a transformer will be
instrumental for achieving excellent distortion performance.
Common-mode errors, such as even-order harmonics or
noise, can be substantially reduced. This is particularly the
case with high output frequencies and/or output amplitudes
below full-scale.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
FIGURE 2. Equivalent Analog Output.
The signal voltage swing that may develop at the two
outputs, I
OUT
and I
OUT
, is limited by a negative and positive
compliance. The negative limit of 1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC902, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
+V
D
= 5V. Note that the compliance range decreases to
about 1V for a selected output current of I
OUTFS
= 2mA.
Care should be taken that the configuration of DAC902 does
not exceed the compliance range to avoid degradation of the
distortion performance and integral linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50
doubly-terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC902 by selecting a suitable
transformer while maintaining optimum voltage levels at
OUTPUT CONFIGURATIONS
The current output of the DAC902 allows for a variety of
configurations, some of which are illustrated below. As men-
tioned previously, utilizing the converter's differential out-
puts will yield the best dynamic performance. Such a differ-
ential output circuit may consist of an RF transformer or a
differential amplifier configuration. The transformer configu-
ration is ideal for most applications with ac coupling, while
op amps will be suitable for a DC-coupled configuration.
The single-ended configuration may be considered for appli-
cations requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground will convert
the output current into a ground-referenced voltage signal.
To improve on the DC linearity, an I-to-V converter can be
used instead. This will result in a negative signal excursion
and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance (see
Figure 3). The appropriate transformer should be carefully
selected based on the output frequency spectrum and imped-
ance requirements. The differential transformer configura-
tion has the benefit of significantly reducing common-mode
signals, thus improving the dynamic performance over a
wide range of frequencies. Furthermore, by selecting a
suitable impedance ratio (winding ratio), the transformer can
be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown in Figure 3 has a 1:1 ratio and may be used
to interface the DAC902 to a 50
load. This results in a 25
load for each of the outputs, I
OUT
and I
OUT
. The output
signals are ac coupled and inherently isolated because of its
magnetic coupling.
INPUT CODE (D11 - D0)
I
OUT
I
OUT
1111 1111 1111
20mA
0mA
1000 0000 0000
10mA
10mA
0000 0000 0000
0mA
20mA
TABLE I. Input Coding vs Analog Output Current.
V
OUTDIFF
=
V
OUT
V
OUT
=
(2
Code 4095)
4096
I
OUTFS
R
LOAD
I
OUT
I
OUT
DAC902
R
L
R
L
+V
A
DAC902
13
SBAS094B
As shown in Figure 3, the transformer's center tap is con-
nected to ground. This forces the voltage swing on I
OUT
and
I
OUT
to be centered at 0V. In this case the two resistors, R
S
,
may be replaced with one, R
DIFF
, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at R
S
I
OUTFS
/2. However, in
this case, the two resistors (R
S
) must be used to enable the
necessary DC-current flow for both outputs.
The OPA680 is configured for a gain of two. Therefore,
operating the DAC902 with a 20mA full-scale output will
produce a voltage output of 1V. This requires the amplifier
to operate off of a dual power supply (5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R
4
.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer solu-
tion because the amplifier introduces another source of dis-
tortion. Suitable amplifiers should be selected based on their
slew-rate, harmonic distortion, and output swing capabilities.
High-speed amplifiers like the OPA680 or OPA687 may be
considered. The ac performance of this circuit may be im-
proved by adding a small capacitor, C
DIFF
, between the
outputs I
OUT
and I
OUT
(as shown in Figure 4). This will
introduce a real pole to create a low-pass filter in order to
slew-limiting the DACs fast output signal steps that other-
wise could drive the amplifier into slew-limitations or into an
overload condition; both would cause excessive distortion.
The difference amplifier can easily be modified to add a level
shift for applications requiring the single-ended output volt-
age to be unipolar, i.e., swing between 0V and +2V.
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the
OPA2680, which is set up as a transimpedance stage, or
I-to-V converter. With this circuit, the DAC's output will be
kept at a virtual ground, minimizing the effects of output
impedance variations, which results in the best DC linearity
(INL). However, as mentioned previously, the amplifier
may be driven into slew-rate limitations, and produce un-
wanted distortion. This may occur especially at high DAC
update rates.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC902 generates a differential output
signal of 0.5Vp-p at the load resistors, R
L
. The resistor
values shown were selected to result in a symmetric 25
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resis-
tors R
L
, and should be considered.
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
1/2
OPA2680
1/2
OPA2680
DAC902
V
OUT
= I
OUT
R
F
V
OUT
= I
OUT
R
F
R
F1
R
F2
C
F1
C
F2
C
D1
C
D2
I
OUT
I
OUT
50
50
5V
+5V
I
OUT
I
OUT
DAC902
R
L
26.1
R
L
28.7
R
4
402
R
3
200
R
2
402
R
1
200
OPA680
C
OPT
+5V
V
OUT
5V
DAC902
I
OUT
I
OUT
1:1
ADT1-1WT
(Mini-Circuits)
R
S
50
R
S
50
R
L
Optional
R
DIFF
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DAC902
14
SBAS094B
The DC gain for this circuit is equal to feedback resistor R
F
.
At high frequencies, the DAC output impedance (C
D1
, C
D2
)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
C
F
is added across R
F
to compensate for this noise-gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
1
2
R
F
C
F
=
GBP
4
R
F
C
D
(8)
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f
-3dB
of approximately:
f
-
3dB
=
GBP
2
R
F
C
D
(9)
The full-scale output voltage is simply defined by the prod-
uct of I
OUTFS
R
F
, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
R
F
and/or I
OUTFS
should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680's output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50
resistor
connected to I
OUT
, providing the termination of the further
connected 50
cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25
load.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, I
OUTFS
, and the load resistor may be mutually
adjusted to provide the desired output signal swing and
performance.
FIGURE 6. Driving a Doubly-Terminated 50
Cable Directly.
I
OUT
I
OUT
DAC902
25
50
50
I
OUTFS
= 20mA
V
OUT
= 0V to +0.5V
FIGURE 7. Internal Reference Configuration.
INTERNAL REFERENCE OPERATION
The DAC902 has an on-chip reference circuit that comprises
a 1.24V bandgap reference and a control amplifier. Ground-
ing pin 16, INT/EXT, enables the internal reference opera-
tion. The full-scale output current, I
OUTFS
, of the DAC902 is
determined by the reference voltage, V
REF
, and the value of
resistor R
SET
. I
OUTFS
can be calculated by:
I
OUTFS
= 32 I
REF
= 32 V
REF
/ R
SET
(10)
As shown in Figure 7, the external resistor R
SET
connects to
the FSA pin (Full-Scale Adjust). The reference control am-
plifier operates as a V-to-I converter producing a reference
current, I
REF
, which is determined by the ratio of V
REF
and
R
SET
, as shown in Equation 10. The full-scale output current,
I
OUTFS
, results from multiplying I
REF
by a fixed factor of 32.
Using the internal reference, a 2k
resistor value results in
a 20mA full-scale output. Resistors with a tolerance of 1%
or better should be considered. Selecting higher values, the
converter output can be adjusted from 20mA down to 2mA.
Operating the DAC902 at lower than 20mA output currents
may be desirable for reasons of reducing the total power
consumption, improving the distortion performance, or ob-
serving the output compliance voltage limitations for a given
load condition.
It is recommended to bypass the REF
IN
pin with a ceramic chip
capacitor of 0.1F or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
3MHz. To improve the ac performance, an additional capacitor
(C
COMPEXT
) should be applied between the BW pin and the
analog supply, +V
A
, as shown in Figure 7. Using a 0.1F
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps
shunting feedthrough signals more effectively, and improving
the noise performance of the DAC902.
DAC902
C
COMPEXT
0.1
F
C
COMP
400pF
+1.24V Ref.
R
SET
2k
0.1
F
INT/EXT
FSA
BW
+5V
+V
A
REF
IN
Current
Sources
I
REF
=
V
REF
R
SET
Ref
Control
Amp
DAC902
15
SBAS094B
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
HIGH (+V
A
) to pin INT/EXT. An external reference voltage
can then be driven into the REF
IN
pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1F capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REF
IN
, has a high input
impedance (1M
) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D11 (MSB) of the
DAC902 accepts standard-positive binary coding. The digi-
tal input word is latched into a master-slave latch with the
rising edge of the clock. The DAC output becomes updated
with the following falling clock edge (refer to the specifica-
tion table and timing diagram for details). The best perfor-
mance will be achieved with a 50% clock duty cycle,
however, the duty cycle may vary as long as the timing
specifications are met. Additionally, the setup and hold
times may be chosen within their specified limits.
All digital inputs are CMOS compatible. The logic thresh-
olds depend on the applied digital supply voltage such that
they are set to approximately half the supply voltage;
V
th
= +V
D
/2 (20% tolerance). The DAC902 is designed to
operate over a supply range of 2.7V to 5.5V.
FIGURE 8. External Reference Configuration.
POWER-DOWN MODE
The DAC902 features a power-down function that can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic
HIGH to the PD pin will initiate the power-down mode,
while a logic LOW enables normal operation. When left
unconnected, an internal active pull-down circuit will enable
the normal operation of the converter.
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
The DAC902 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+V
A
)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1uF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. There-
fore, they should be located as close as physically possible
to those device leads. Whenever possible, the capacitors
should be located immediately under each pair of supply/
ground pins on the reverse side of the pc-board. This layout
approach will minimize the parasitic inductance of compo-
nent leads and pcb runs.
R
SET
+5V
External
Reference
I
REF
=
V
REF
R
SET
DAC902
C
COMPEXT
0.1
F
C
COMP
400pF
+1.24V Ref.
INT/EXT
FSA
BW
+5V
+V
A
REF
IN
Current
Sources
Ref
Control
Amp
DAC902
16
SBAS094B
Further supply decoupling with surface mount tantalum
capacitors (1uF to 4.7uF) may be added as needed in
proximity of the converter.
Low noise is required for all supply and ground connections
to the DAC902. It is recommended to use a multilayer pc-
board utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of
the different supply currents and signal traces. Generally,
analog supply and ground planes should only extend into
analog signal areas, such as the DAC output signal and the
reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can
be realized with a short track of approximately 1/8" (3mm).
The power to the DAC902 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc-board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +V
A
supply pin of the DAC902.
While designing the layout, it is important to keep the analog
signal traces separate from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC902
17
SBAS094B
PACKAGE DRAWINGS
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DAC902E
ACTIVE
TSSOP
PW
28
52
DAC902E/2K5
ACTIVE
TSSOP
PW
28
2500
DAC902U
ACTIVE
SOIC
DW
28
28
DAC902U/1K
ACTIVE
SOIC
DW
28
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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