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FEATURES
APPLICATIONS
DESCRIPTION
_
+
+
_
V
ref
OSC
+
PWM
BIAS
POR
ISO722
Only
Filter
Pulse Width
Demodulation
Carrier Detect
_
+
_
+
Input
+
Filter
Data MUX
AC Detect
3-State
Output Buffer
IN
EN
Isolation Barrier
DC Channel
AC Channel
FUNCTION DIAGRAM
OUT
V
ref
POR
ISO721, ISO721M
ISO722, ISO722M
SLLS629B JANUARY 2006 REVISED MAY 2006
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
Drop-In Replacement for Most Opto and
Magnetic Isolators
4000-V
(peak)
Isolation
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1 and CSA Approved
Industrial Fieldbus
50 kV/s Transient Immunity Typical
Modbus
Signaling Rate 0 Mbps to 150 Mbps
Profibus
Low-Propagation Delay
DeviceNetTM Data Buses
Low-Pulse Skew (Pulse-Width Distortion)
Smart Distributed Systems (SDSTM)
Low-Power Sleep Mode
Computer Peripheral Interface
High-Electromagnetic Immunity
Servo Control Interface
Low-Input Current Requirement
Data Acquisition
Failsafe Output
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO
2
) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets
or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to
ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 s, the input is
assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high
state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
GND2
1
2
3
4
8
7
6
5
V
CC1
IN
V
CC1
GND1
V
CC2
OUT
GND2
Isolation
EN
1
2
3
4
8
7
6
5
V
CC1
IN
V
CC1
GND1
V
CC2
OUT
GND2
Isolation
ISO721, ISO721M
ISO722, ISO722M
SLLS629B JANUARY 2006 REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive
matching, and allows fast transient voltage changes between the input and output grounds without corrupting the
output. The small capacitance and resulting time constant provide for fast operation with signaling rates
(1)
from 0
Mbps (dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO722 and ISO722M devices includes an active-low output enable that when driven to a high-logic level,
places the output in a high-impedance state, and turns off internal bias circuitry to conserve power.
Both the ISO721 and ISO722 have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M and ISO722M have CMOS V
CC
/2 input thresholds, but do not have the noise-filter and the
additional propagation delay. These features of the ISO721M also provide for reduced jitter operation.
The ISO721, ISO721M, ISO722, and ISO722M are characterized for operation over the ambient temperature
range of 40C to 125C.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in
the units bps (bits per second).
PACKAGE PIN ASSIGMENTS
PACKAGE PIN ASSIGMENTS
ISO721D, ISO721MD
ISO722D, ISO722MD
(TOP VIEW)
(TOP VIEW)
AVAILABLE OPTIONS
OUTPUT
INPUT
NOISE
MARKED
PRODUCT
PACKAGE
(1)
ORDERING NUMBER
GREEN
ENABLED
THRESHOLDS
FILTER
AS
ISO721D (rail)
ISO721
NO
TTL
YES
SOIC-8
ISO721
ISO721DR (reel)
ISO721MD (rail)
ISO721M
NO
CMOS
NO
SOIC-8
IS721M
ISO721MDR (reel)
Pb Free
Sb/Br Free
ISO722D (rail)
ISO722
YES
TTL
YES
SOIC-8
ISO722
ISO722DR (reel)
ISO722MD (rail)
ISO722M
YES
CMOS
NO
SOIC-8
IS722M
ISO722MDR (reel)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
www.ti.com
.
REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Recognized under 1577
Certified according to IEC 60747-5-2
Acceptance Notice: CA-5A
Component Recognition Program
(1)
File Number: 40014131
File Number: 1698195
File Number: E181974
(1)
Production tested
3000 V
RMS
for 1 second in accordance with UL 1577.
2
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
IEC 60747-5-2 INSULATION CHARACTERISTICS
(1)
ISO721, ISO721M
ISO722, ISO722M
SLLS629B JANUARY 2006 REVISED MAY 2006
UNIT
V
CC
Supply voltage
(2)
, V
CC1
, V
CC2
0.5 V to 6 V
V
I
Voltage at IN, OUT, or EN terminal
0.5 V to 6 V
I
O
Output Current
15 mA
Human Body Model
JEDEC Standard 22, Test Method A114-C.01
2 kV
Electrostatic
ESD
All pins
discharge
Charged Device Model
JEDEC Standard 22, Test Method C101
1 kV
T
J
Maximum junction temperature
170C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
MIN
TYP
MAX
UNIT
4.5
5.5
V
CC
Supply voltage, V
CC1
, V
CC2
V
3
3.6
I
OH
4
Output current
mA
I
OL
-4
ISO72x
10
t
ui
Input pulse width
ns
ISO72xM
6.67
V
IH
High-level input voltage (IN, EN)
2
V
CC
ISO72x
V
V
IL
Low-level input voltage (IN, EN)
0
0.8
V
IH
High-level input voltage (IN, EN)
0.7 V
CC
V
CC
IOS72xM
V
V
IL
Low-level input voltage (IN, EN)
0
0.3 V
CC
T
J
Junction temperature
See the Thermal Characteristics table
150
C
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
H
1000
A/m
certification
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
V
IORM
Maximum working insulation voltage
560
V
After Input/Output Safety Test Subgroup 2/3
V
PR
= V
IORM
1.2, t = 10 s,
672
V
Partial discharge < 5 pC
Method a, V
PR
= V
IORM
1.6,
V
PR
Input to output test voltage
Type and sample test with t = 10 s,
896
V
Partial discharge < 5 pC
Method b1, V
PR
= V
IORM
1.875,
100 % Production test with t = 1 s,
1050
V
Partial discharge < 5 pC
V
IOTM
Transient overvoltage
t = 60 s
4000
V
R
S
Insulation resistance
V
IO
= 500 V at T
S
>10
9
Pollution degree
2
(1)
Climatic Classification 40/125/21
3
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ELECTRICAL CHARACTERISTICS: V
CC1
and V
CC2
5-V OPERATION
SWITCHING CHARACTERISTICS: V
CC1
and V
CC2
5-V OPERATION
ISO721, ISO721M
ISO722, ISO722M
SLLS629B JANUARY 2006 REVISED MAY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent
0.5
1
I
CC1
V
CC1
supply current
V
I
= V
CC
or 0 V, No load
mA
25 Mbps
2
4
ISO722/722M
EN at V
CC
200
A
Sleep Mode
V
I
= V
CC
or 0 V,
No load
I
CC2
V
CC2
supply current
EN at 0 V or
Quiescent
8
12
ISO721/721M
mA
25 Mbps
V
I
= V
CC
or 0 V, No load
10
14
I
OH
= -4 mA, See
Figure 1
V
CC
0.8
4.6
V
OH
High-level output voltage
V
I
OH
= 20
A, See
Figure 1
V
CC
0.1
5
I
OL
= 4 mA, See
Figure 1
0.2
0.4
V
OL
Low-level output voltage
V
I
OL
= 20
A, See
Figure 1
0
0.1
V
I(HYS)
Input voltage hysteresis
150
mV
I
IH
High-level input current
EN, IN at 2 V
10
A
I
IL
Low-level input current
EN, IN at 0.8 V
10
High-impedance output
I
OZ
ISO722, ISO722M
EN, IN at V
CC
1
A
current
C
I
Input capacitance to ground
IN at V
CC
, V
I
= 0.4 sin (4E6
t)
1
pF
CMTI
Common-mode transient immunity
V
I
= V
CC
or 0 V, See
Figure 5
25
50
kV/
s
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PLH
Propagation delay, low-to-high-level output
13
17
24
t
PHL
Propagation delay , high-to-low-level output
ISO72x
13
17
24
ns
t
sk(p)
Pulse skew |t
PHL
t
PLH
|
0.5
2
EN at 0 V,
See
Figure 1
t
PLH
Propagation delay, low-to-high-level output
8
10
16
t
PHL
Propagation delay, high-to-low-level output
ISO72xM
8
10
16
t
sk(p)
Pulse skew |t
PHL
t
PLH
|
0.5
1
t
sk(pp)
(1)
Part-to-part skew
0
3
ns
t
r
Output signal rise time
1
EN at 0 V,
ns
See
Figure 1
t
f
Output signal fall time
1
Sleep-mode propagation delay,
t
pHZ
6
8
15
ns
high-level-to-high-mpedance output
See
Figure 2
Sleep-mode propagation delay,
t
pZH
3.5
4
8
s
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
t
pLZ
5.5
8
15
ns
low-level-to-high-impedance output
See
Figure 3
Sleep-mode propagation delay,
t
pZL
4
5
8
s
high-impedance-to-low-level output
t
fs
Failsafe output delay time from input power loss
See
Figure 4
3
s
100 Mbps NRZ data input, See
Figure 6
2
ISO72x
100 Mbps unrestricted bit run length data
3
input, See
Figure 6
t
jit(PP)
Peak-to-peak eye-pattern jitter
ns
150 Mbps NRZ data input, See
Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
2
input, See
Figure 6
(1)
t
sk(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: V
CC1
at 5-V, V
CC2
at 3.3-V OPERATION
SWITCHING CHARACTERISTICS: V
CC1
at 5-V, V
CC2
at 3.3-V OPERATION
ISO721, ISO721M
ISO722, ISO722M
SLLS629B JANUARY 2006 REVISED MAY 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent
0.5
1
I
CC1
V
CC1
supply current
V
I
= V
CC
or 0 V, No load
mA
25 Mbps
2
4
ISO722/722M
EN at V
CC
150
A
Sleep Mode
V
I
= V
CC
or 0 V,
No load
I
CC2
V
CC2
supply current
EN at 0 V or
Quiescent
4
6.5
ISO721/721M
mA
25 Mbps
V
I
= V
CC
or 0 V, No load
5
7.5
I
OH
= 4 mA, See
Figure 1
V
CC
0.4
3
V
OH
High-level output voltage
V
I
OH
= 20
A, See
Figure 1
V
CC
0.1
3.3
I
OL
= 4 mA, See
Figure 1
0.2
0.4
V
OL
Low-level output voltage
V
I
OL
= 20
A, See
Figure 1
0
0.1
V
I(HYS)
Input voltage hysteresis
150
mV
I
IH
High-level input current
EN, IN at 2 V
10
A
I
IL
Low-level input current
EN, IN at 0.8 V
10
High-impedance output
I
OZ
ISO722, ISO722M
EN, IN at V
CC
1
A
current
C
I
Input capacitance to ground
IN at V
CC
, V
I
= 0.4 sin (4E6
t)
1
pF
CMTI
Common-mode transient immunity
V
I
= V
CC
or 0 V, See
Figure 5
25
40
kV/
s
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PLH
Propagation delay, low-to-high-level output
15
19
30
t
PHL
Propagation delay , high-to-low-level output
ISO72x
15
19
30
ns
t
sk(p)
Pulse skew |t
PHL
t
PLH
|
0.5
3
EN at 0 V,
See
Figure 1
t
PLH
Propagation delay, low-to-high-level output
10
12
20
t
PHL
Propagation delay, high-to-low-level output
ISO72xM
10
12
20
t
sk(p)
Pulse skew |t
PHL
t
PLH
|
0.5
1
t
sk(pp)
(1)
Part-to-part skew
0
5
ns
t
r
Output signal rise time
2
EN at 0 V,
ns
See
Figure 1
t
f
Output signal fall time
2
Sleep-mode propagation delay,
t
pHZ
7
11
25
ns
high-level-to-high-mpedance output
See
Figure 2
Sleep-mode propagation delay,
t
pZH
4.5
6
8
s
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
t
pLZ
7
13
25
ns
low-level-to-high-impedance output
See
Figure 3
Sleep-mode propagation delay,
t
pZL
4.5
6
8
s
high-impedance-to-low-level output
t
fs
Failsafe output delay time from input power loss
See
Figure 4
3
s
100 Mbps NRZ data input, See
Figure 6
2
ISO72x
100 Mbps unrestricted bit run length data
3
input, See
Figure 6
t
jit(PP)
Peak-to-peak eye-pattern jitter
ns
150 Mbps NRZ data input, See
Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
2
input, See
Figure 6
(1)
t
sk(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
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