MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Low Supply Voltage Range 2.5 V 5.5 V
D
Ultra Low-Power Consumption
D
Low Operation Current, 400
A at 1 MHz,
3 V
D
Five Power Saving Modes: (Standby Mode:
1.3
A, RAM Retention/Off Mode: 0.1
A)
D
Wakeup From Standby Mode in 6
s
Maximum
D
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
D
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
D
Integrated LCD Driver for up to 64 or 92
Segments
D
Slope A/D Converter With External
Components
D
Serial Onboard Programming
D
Program Code Protection by Security Fuse
D
Family Members Include:
MSP430C311S: 2k Byte ROM, 128 Byte RAM
MSP430C312: 4k Byte ROM, 256 Byte RAM
MSP430C313: 8k Byte ROM, 256 Byte RAM
MSP430C314: 12k Byte ROM, 512 Byte RAM
MSP430C315: 16k Byte ROM, 512 Byte RAM
MSP430P313: 8k Byte OTP, 256 Byte RAM
MSP430P315: 16k Byte OTP, 512 Byte RAM
MSP430P315S: 16k Byte OTP, 512 Byte RAM
D
EPROM Version Available for Prototyping :
PMS430E313FZ
, PMS430E315FZ
D
Available in:
56-Pin Plastic Small-Outline Package
(SSOP),
48-Pin SSOP (MSP430C311S,
MSP430P315S),
68-Pin J-Leaded Ceramic Chip Carrier
(JLCC) Package (EPROM Only)
description
The MSP430 is an ultralow-power mixed signal microcontroller family consisting of several devices that feature
different sets of modules targeted to various applications. The microcontroller is designed to be battery operated
for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and
a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator,
together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in
less than 6
m
s.
MSP430P313/E313 not recommended for new designs replaced by MSP430P315/E315.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
NC No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TDO/TDI
TDI/VPP
TMS
TCK
RST/NMI
XBUF
VSS
VCC
R23
R13
Xin
Xout/TCLK
P0.0
P0.1/RXD
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
P0.7
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
CIN
NC
NC
COM3
COM2
COM1
COM0
S27/O27/CMPI
S26/O26
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
S1
S0
DL PACKAGE
(56-PIN TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TDI/VPP
TMS
TCK
RST/NMI
XBUF
VSS
VCC
R23
R13
Xin
Xout/TCLK
P0.1/RXD
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
NC
TP0.0
TP0.1
TP0.2
TP0.3
TP0.5
CIN
TDO/TDI
COM3
COM2
COM1
COM0
S27/O27/CMPI
NC
VSS
NC
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
DL PACKAGE
(48-PIN TOP VIEW)
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Typical applications include sensor systems that capture analog signals, converting them to digital values, and
then processes the data and displays them or transmits them to a host system. The timer/port module provides
single-slope A/D conversion capability for resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SSOP
48-Pin
(DL)
SSOP
56-Pin
(DL)
JLCC
68-Pin
(FZ)
40
C to 85
C
MSP430C311SIDL
MSP430C312IDL
MSP430C313IDL
MSP430C314IDL
40
C to 85
C
MSP430P315SIDL
MSP430C315IDL
MSP430P313IDL
MSP430P315IDL
25
C
PMS430E313FZ
25
C
--
--
PMS430E315FZ
MSP430P313/E313 not recommended for new designs replaced by MSP430P315/E315.
functional block diagram
MSP430C312,313,314,315 and MSP430P313
,315 and PMS430E313,315
Oscillator
FLL
System Clock
ACLK
MCLK
4/8/12/16 kB
ROM
8/16 kB
C: ROM
256/512 B
RAM
Power-On-
Reset
8-Bit Timer/
Counter
Serial Protocol
I/O Port
8 I/O's, All With
Interr. Cap.
3 Int. Vectors
CPU
Incl. 16 Reg.
Test
JTAG
Bus
Conv
Timer/Port
Applications:
Timer, O/P
Basic
LCD
92 Segments
1, 2, 3, 4 MUX
Timer1
Watchdog
Timer
15/16 Bit
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
5
LCD
f
CMPI
TP0.04
CIN
XIN
Xout
XBUF
RST/NMI
P0.07
Com03
S018,22,23,26/
S27/O27/CMPI
R13
R23
TDI/VPP
TDO/TDI
TMS
TCK
TXD
P: OTP
A/D Conv.
Support
RXD
OPT or EPROM
E: EPROM
8
TP0.5
O218,22,23,26
VCC
V SS
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
MSP430C312, MSP430C313
, MSP430C314, MSP430C315, MSP430P313
, MSP430P315
56-pin SSOP package
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CIN
27
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
COM0 COM3
52 55
O
Common output pins. COM0 COM3 are used for LCD back planes.
P0.0
13
I/O
General-purpose digital I/O pin
P0.1/RXD
14
I/O
General-purpose digital I/O pin, receive data input port 8-bit (timer/counter)
P0.2/TXD
15
I/O
General-purpose digital I/O pin, transmit data output port 8-bit (timer/counter)
P0.3 P0.7
16 20
I/O
Five general-purpose digital I/O pins, bit 37
R23
9
I
Input of second positive analog LCD level (V2) (LCD)
R13
10
I
Input of third positive analog LCD level (V3 of V4) (LCD)
RST/NMI
5
I
Reset input or nonmaskable interrupt input
S0
29
O
Segment line S0 (LCD)
S1
30
O
Segment line S1 (LCD)
S2/O2 S5/O5
31 34
O
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6 S9/O9
35 38
O
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10 S13/O13
39 42
O
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14 S17/O17
43 46
O
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
S18/O18
47
O
Segment line (S18) or digital output port O18 , group 5 (LCD)
S22/O22 S23/O23
48,49
O
Segment lines (S22 to S23) or digital output port O22 to O23, group 6 (LCD)
S26/O26
50
O
Segment line (S26) or digital output port O26, group 7 (LCD)
S27/O27/CMPI
51
I/O
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
4
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
2
I
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI
1
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
3
I
Test mode select. TMS is an input terminal for device programming and test.
TP0.0
21
O/Z
General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1
22
O/Z
General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2
23
O/Z
General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3
24
O/Z
General-purpose 3-state digital output port, bit 3( timer/port)
TP0.4
25
O/Z
General-purpose 3-state digital output port, bit 4 (timer/port)
TP0.5
26
I/O/Z
General-purpose 3-state digital I/O pin, bit 5 (timer/port)
VCC
8
Supply voltage
VSS
7
Ground reference
XBUF
6
O
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Xin
11
I
Input terminal of crystal oscillator
Xout/TCLK
12
I/O
Output terminal of crystal oscillator or test clock input
MSP430P313/E313 not recommended for new designs replaced by MSP430P315/E315.
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
MSP430C311S and MSP430P315S
P0.16
6
Oscillator
FLL
System Clock
ACLK
MCLK
2 kB
ROM
16 kB
C: ROM
128/512B
RAM
Power-On-
Reset
8-bit Timer/
Counter
Serial Protocol
I/O Port
6 I/O's, All With
Interr. Cap.
2 Int. Vectors
CPU
Incl. 16 Reg.
Test
JTAG
Bus
Conv
Timer/Port
Applications:
Timer, O/P
Basic
LCD
64 Segments
1, 2, 3, 4 MUX
Timer1
Watchdog
Timer
15/16 Bit
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
4
LCD
f
CMPI
TP0.03
CIN
XIN
Xout
XBUF
RST/NMI
COM03
S216/O216
S27/O27/CMPI
R13
R23
TDI/VPP
TDO/TDI
TMS
TCK
TXD
P: OTP
A/D Conv.
Support
RXD
OTP
TP0.5
VCC
V SS
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D FEBRUARY 1998 REVISED APRIL 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
MSP430C311S, MSP430P315S
48-pin SSOP package
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CIN
24
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
COM0 COM3
44 47
O
Common output pins, COM0 COM3 are used for LCD back planes.
P0.1/RXD
12
I/O
General-purpose digital I/O pin, receive data input port 8-Bit (timer/counter)
P0.2/TXD
13
I/O
General-purpose digital I/O pin, transmit data output port 8-Bit (timer/counter)
P0.3
14
I/O
General-purpose digital I/O pins, bit 3
P0.4
15
I/O
General-purpose digital I/O pins, bit 4
P0.5
16
I/O
General-purpose digital I/O pins, bit 5
P0.6
17
I/O
General-purpose digital I/O pins, bit 6
R23
8
I
Input of second positive analog LCD level (V2) (LCD)
R13
9
I
Input of third positive analog LCD level (V3 of V4) (LCD)
RST/NMI
4
I
Reset input or nonmaskable interrupt input
S2/O2 S5/O5
25 28
O
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6 S9/O9
29 32
O
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10 S13/O13
33 36
O
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14 S16/O16
37 39
O
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
S27/O27/CMPI
43
I/O
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
3
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
1
I
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI
48
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
2
I
Test mode select. TMS is an input terminal for device programming and test.
TP0.0
19
O/Z
General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1
20
O/Z
General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2
21
O/Z
General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3
22
O/Z
General-purpose 3-state digital output port, bit 3 (timer/port)
TP0.5
23
I/O/Z
General-purpose 3-state digital I/O pin, bit 5 (timer/port)
VCC
7
Supply voltage
VSS
6, 41
Ground references
XBUF
5
O
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Xin
10
I
Input terminal of crystal oscillator
Xout/TCLK
11
I/O
Output terminal of crystal oscillator or test clock input
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