MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A FEBRUARY 1998 REVISED MARCH 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Low Supply Voltage Range, 2.7 V 5.5 V
D
Low Operation Current, 3 mA at 1 MHz,
3 V
D
Ultralow Power Consumption (Standby
Mode Down to 0.1
m
A)
D
Five Power-Saving Modes
D
Wakeup From Standby Mode in 6
m
s
D
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
D
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
D
Integrated LCD Driver for up to 84
Segments
D
Integrated 12+2 Bit A/D Converter
D
Family Members Include:
MSP430P325, 16KB OTP, 512 Byte RAM
D
EPROM Version Available for Prototyping:
PMS430E325
D
Serial Onboard Programming
D
Programmable Code Protection by Security
Fuse
D
Avaliable in 64 Pin Quad Flatpack (QFP),
68 Pin Plastic J-Leaded Chip Carrier
(PLCC), 68 Pin J-Leaded Ceramic Chip
Carrier (JLCC) Package (EPROM Version)
description
The Texas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several
devices which feature different sets of modules targeted to various applications. The microcontroller is designed
to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated
registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally-
controlled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode
to active mode in less than 6
m
s.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20 2122 23 24 25 26 272829 30 31 32
64 63 6261 60 59 58 57 56 55 54 5352
PG Package
(TOP VIEW)
AV
CC
DV
CC
SV
CC
Rext
A2
A3
A4
A5
Xin
Xout/TCLK
CIN
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
P0.0
P0.1/RXD
COM0
S20/O20/CMPI
S19/O19
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
DV
SS
AV
SS
A1
A0
XBUF
RST/NMI
TCK
TMS
TDI/VPP
TDO/TDI
COM3
COM2
COM1
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
P0.7
R33
R23
R13
R03
S0
S1
S2/O2
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A FEBRUARY 1998 REVISED MARCH 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated
12+2 bit A/D converter with six multiplexed inputs.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC
64-PIN QFP
(PG)
PLASTIC
64-PIN QFP
(PM)
PLASTIC
68-PIN PLCC
(FN)
CERAMIC
68-PIN JLCC
(FZ)
40
C to 85
C
MSP430P325IPG
MSP430P325IPM
MSP430P325IFN
40
C to 85
C
MSP430P325IPG
MSP430P325IPM
MSP430P325IFN
--
25
C
PMS430E325FZ
25
C
--
--
--
PMS430E325FZ
functional block diagram
Oscillator
FLL
System Clock
ACLK
MCLK
8/16 kB ROM
16 kB OTP
'C': ROM
256/512 B
RAM
Power-on-
Reset
8 b Timer/
Counter
Serial Protocol
I/O Port
8 I/O's, All With
Interr. Cap.
3 Int. Vectors
CPU
Incl. 16 Reg.
Test
JTAG
Bus
Conv
Timer/Port
Applications:
Timer, O/P
Basic
LCD
84 Segments
1, 2, 3, 4 MUX
Timer1
ADC
12 + 2 Bit
6 Channels
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
6
LCD
f
CMPI
TP0.05
CIN
XIN Xout/TCLK
XBUF
P0.0
P0.7
Com03
S019/O219
S20/O20CMPI
R33
R13
TDI/VPP
TDO/TDI
TMS
TCK
TXD
'P': OTP
A/D Conv.
Support
RXD
Watchdog
Timer
15/16 Bit
Current S.
6
A05
Rext
SVCC
RST/NMI
R23
R03
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A FEBRUARY 1998 REVISED MARCH 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVCC
1
Positive analog supply voltage
AVSS
63
Analog ground reference
A0
61
I
Analog-to-digital converter input port 0 or digital input port 0
A1
62
I
Analog-to-digital converter input port 1 or digital input port 1
A2A5
58
I
Analog-to-digital converter inputs ports 25 or digital inputs ports 25
CIN
11
I
Input used as enable of counter TPCNT1 Timer/Port
COM03
5154
O
Common outputs, used for LCD backplanes LCD
DVCC
2
Positive digital supply voltage
DVSS
64
Digital ground reference
P0.0
18
I/O
General-purpose digital I/O
P0.1/RXD
19
I/O
General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter
P0.2/TXD
20
I/O
General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter
P0.3P0.7
2125
I/O
Five general-purpose digital I/Os, bit 3 to bit 7
Rext
4
I
Programming resistor input of internal current source
RST/NMI
59
I
Reset input or non-maskable interrupt input
R03
29
I
Input of fourth positive analog LCD level (V4) LCD
R13
28
I
Input of third positive analog LCD level (V3) LCD
R23
27
I
Input of second positive analog LCD level (V2) LCD
R33
26
O
Output of first positive analog LCD level (V1) LCD
SVCC
3
Switched AVCC to analog-to-digital converter
S0
30
O
Segment line S0 LCD
S1
31
O
Segment line S1 LCD
S2S5/O2O5
3235
O
Segment lines S2 to S5 or digital output ports O2O5, group 1 LCD
S20/O20/CMPI
50
I/O
Segment line S20 can be used as comparator input port CMPI Timer/Port
S6S9/O6O9
3639
O
Segment lines S6 to S9 or digital output ports O6O9, group 2 LCD
S10S13/O10O13
4043
O
Segment lines S10 to S13 or digital output ports O10O13, group 3 LCD
S14S17/O14O17
4447
O
Segment lines S14 to S17 or digital output ports O14 to O17, group 4 LCD
S18-S19/O18-O19
48, 49
O
Segment lines S18 and S19 or digital output port O18 and O19, group 5 LCD
TCK
58
I
Test clock, clock input terminal for device programming and test
TDO/TDI
55
I/O
Test data output, data output terminal or data input during programming
TDI/VPP
56
I
Test data input, data input terminal or input of programming voltage
TMS
57
I
Test mode select, input terminal for device programming and test
TP0.0
12
O
General-purpose 3-state digital output port, bit 0 Timer/Port
TP0.1
13
O
General-purpose 3-state digital output port, bit 1 Timer/Port
TP0.2
14
O
General-purpose 3-state digital output port, bit 2 Timer/Port
TP0.3
15
O
General-purpose 3-state digital output port, bit 3 Timer/Port
TP0.4
16
O
General-purpose 3-state digital output port, bit 4 Timer/Port
TP0.5
17
I/O
General-purpose digital input/output port, bit 5 Timer/Port
XBUF
60
O
Clock signal output of system clock MCLK or crystal clock ACLK
Xin
9
I
Input terminal of crystal oscillator
Xout/TCLK
10
I/O
Output terminal of crystal oscillator or test clock input
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A FEBRUARY 1998 REVISED MARCH 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
short-form description
processing unit
The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and it is
distinguished by ease of programming. All operations other than program-flow instructions are consequently
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.
CPU
Sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor frequency.
Four of the registers are reserved for special
use as a program counter, a stack pointer, a status
register, and a constant generator. The remaining
registers are available as general-purpose
registers.
Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory
manipulation.
instruction set
The instruction set for this register-register architecture provides a powerful and easy-to-use assembler
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4, R5
R4 + R5
R5
Single operands, destination only
e.g. CALL R8
PC
(TOS), R8
PC
Relative jump, un-/conditional
e.g. JNE
Jump-on equal bit = 0
Each instruction that operates on word and byte data is identified by the suffix B.
Examples:
Instructions for word operation
Instructions for byte operation
MOV
EDE, TONI
MOV.B
EDE, TONI
ADD
#235h, &MEM
ADD.B
#35h, &MEM
PUSH
R5
PUSH.B
R5
SWPB
R5
--
Program Counter
General-Purpose Register
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
R5
General-Purpose Register
R14
General-Purpose Register
R15
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A FEBRUARY 1998 REVISED MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 2. Address Mode Descriptions
ADDRESS MODE
s
d
SYNTAX
EXAMPLE
OPERATION
Register
MOV Rs, Rd
MOV R10, R11
R10
R11
Indexed
MOV X(Rn), Y(Rm)
MOV 2(R5), 5(R6)
M(2 + R5)
M(6 + R6)
Symbolic (PC relative)
MOV EDE, TONI
M(EDE)
M(TONI)
Absolute
MOV &MEM, &TCDAT
M(MEM)
M(TCDAT)
Indirect
MOV @Rn, Y(Rm)
MOV @R10, Tab(R6)
M(R10)
M(Tab + R6)
Indirect autoincrement
MOV @Rn+, RM
MOV @R10+, R11
M(R10)
R11, R10 + 2
R10
Immediate
MOV #X, TONI
MOV #45, TONI
#45
M(TONI)
NOTE: s = source d = destination
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
indirect addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The software can configure five operating modes:
D
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D
Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D
Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D
Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D
Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(
MCLK generator) is switched off.
D
Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
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