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Электронный компонент: MSP430X12X2

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MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Low Supply Voltage Range 1.8 V to 3.6 V
D
Ultralow-Power Consumption:
- Active Mode: 200
A at 1 MHz, 2.2 V
- Standby Mode: 0.7
A
- Off Mode (RAM Retention): 0.1
A
D
Five Power Saving Modes
D
Wake-Up From Standby Mode in less
than 6
s
D
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
D
Basic Clock Module Configurations:
- Various Internal Resistors
- Single External Resistor
- 32-kHz Crystal
- High Frequency Crystal
- Resonator
- External Clock Source
D
16-Bit Timer_A With Three
Capture/Compare Registers
D
10-Bit, 200-ksps A/D Converter With
Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller
D
Serial Communication Interface (USART0)
With Software-Selectable Asynchronous
UART or Synchronous SPI
(MSP430x12x2 Only)
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
D
Supply Voltage Brownout Protection
D
MSP430x11x2 Family Members Include:
MSP430F1122: 4KB + 256B Flash Memory
256B RAM
MSP430F1132: 8KB + 256B Flash Memory
256B RAM
Available in 20-Pin Plastic SOWB, 20-Pin
Plastic TSSOP and 32-Pin QFN Packages
D
MSP430x12x2 Family Members Include:
MSP430F1222: 4KB + 256B Flash Memory
256B RAM
MSP430F1232: 8KB + 256B Flash Memory
256B RAM
Available in 28-Pin Plastic SOWB, 28-Pin
Plastic TSSOP, and 32-Pin QFN Packages
D
For Complete Module Descriptions, See the
MSP430x1xx Family User's Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6
s.
The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal microcontrollers with a built-in
16-bit timer, 10-bit A/D converter with integrated reference and data transfer controller (DTC) and fourteen or
twenty-two I/O pins. In addition, the MSP430x12x2 series microcontrollers have built-in communication
capability using asynchronous (UART) and synchronous (SPI) protocols.
Digital signal processing with the 16-bit RISC performance enables effective system solutions such as glass
breakage detection with signal analysis (including wave digital filter algorithm). Another area of application is
in stand-alone RF sensors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002 - 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 20-PIN
SOWB (DW)
PLASTIC 20-PIN
TSSOP (PW)
PLASTIC 28-PIN
SOWB (DW)
PLASTIC 28-PIN
TSSOP (PW)
PLASTIC 32-PIN
QFN (RHB)
MSP430F1122IDW
MSP430F1122IPW
MSP430F1222IDW
MSP430F1222IPW
MSP430F1122IRHB
MSP430F1132IRHB
- 40
C to 85
C
MSP430F1122IDW
MSP430F1132IDW
MSP430F1122IPW
MSP430F1132IPW
MSP430F1222IDW
MSP430F1232IDW
MSP430F1222IPW
MSP430F1232IPW
MSP430F1132IRHB
MSP430F1222IRHB
MSP430F1232IRHB
pin designation, MSP430x11x2 (see Notes 1, 2 and 3)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST
V
CC
P2.5/R
OSC
V
SS
XOUT
XIN
RST/NMI
P2.0/ACLK/A0
P2.1/INCLK/A1
P2.2/TA0/A2
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V
REF+
/V
eREF+
P2.3/TA1/A3/V
REF-
/V
eREF-
DW or PW PACKAGE
(TOP VIEW)
RHB PACKAGE
(TOP VIEW)
XIN
P2.5/R
OSC
NC
NC
RST/NMI
V
CC
P2.0/ACLK/A0
TEST
P2.1/INCLK/A1
P1.7/T
A2/TDO/TDI
XOUT
P1.6/T
A1/TDI/TCLK
P1.1/TA0
P1.0/TACLK/ADC10CLK
NC
P2.4/TA2/A4/V
REF+
/V
eREF+
P2.3/TA1/A3/V
REF-
/V
eREF-
P1.2/TA1
1
10 11 12 13
27
28
29
P1.5/T
A0/TMS
2
5
7
6
3
4
14
30
31
V
SS
P1.3/TA2
8
24
23
20
18
19
22
21
17
26
15
P2.2/TA0/A2
NC
P1.4/SMCLK/TCK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NOTES:
1. NC pins are not internally connected. Recommended connection to V
SS
.
2. Recommended connection to V
SS
for all pins labeled "Reserved" to avoid floating nodes, otherwise increased current
consumption may occur.
3. Power pad connection to V
SS
recommended.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pin designation, MSP430x12x2 (see Notes 1 and 2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DW or PW PACKAGE
(TOP VIEW)
TEST
V
CC
P2.5/R
OSC
V
SS
XOUT
XIN
RST/NMI
P2.0/ACLK/A0
P2.1/INCLK/A1
P2.2/TA0/A2
P3.0/STE0/A5
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V
REF+
/V
eREF+
P2.3/TA1/A3/V
REF-
/V
eREF-
P3.7/A7
P3.6/A6
P3.5/URXD0
P3.4/UTXD0
RHB PACKAGE
(TOP VIEW)
XIN
P2.5/R
OSC
NC
NC
RST/NMI
V
CC
P2.0/ACLK/A0
TEST
P2.1/INCLK/A1
P1.7/T
A2/TDO/TDI
XOUT
P1.6/T
A1/TDI/TCLK
P1.1/TA0
P1.0/TACLK/ADC10CLK
NC
P2.4/TA2/A4/V
REF+
/V
eREF+
P2.3/TA1/A3/V
REF-
/V
eREF-
P1.2/TA1
1
10 11 12 13
27
28
29
P3.0/STE0/A5
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P3.5/URXD0
P3.6/A6
P1.5/T
A0/TMS
2
5
7
6
3
4
14
30
31
V
SS
P1.3/TA2
8
24
23
20
18
19
22
21
17
26
15
P2.2/TA0/A2
NC
P3.7/A7
P1.4/SMCLK/TCK
NOTES:
1. NC pins are not internally connected. Recommended connection to V
SS
.
2. Power pad connection to V
SS
recommended.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram, MSP430x11x2
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN
XOUT
P2
MDB, 16 Bit
MAB, 16 Bit
MCLK
MAB,
4 Bit
V
CC
V
SS
RST/NMI
System
Clock
R
OSC
P1/JTAG
8KB Flash
4KB Flash
256B RAM
256B RAM
ADC10
10-Bit
Autoscan
DTC
Watchdog
Timer
15/16-Bit
Timer_A3
3 CC Reg
I/O Port 1
8 I/Os, with
Interrupt
Capability
I/O Port 2
6 I/Os, with
Interrupt
Capability
POR/
Brownout
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
TEST
Test
JTAG
Emulation
Module
8
6
functional block diagram, MSP430x12x2
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN
XOUT
P3
P2
MDB, 16 Bit
MAB, 16 Bit
MCLK
MAB,
4 Bit
V
CC
V
SS
RST/NMI
System
Clock
R
OSC
P1/JTAG
8KB Flash
4KB Flash
256B RAM
256B RAM
ADC10
10-Bit
Autoscan
DTC
Watchdog
Timer
15/16-Bit
Timer_A3
3 CC Reg
I/O Port 1
8 I/Os, with
Interrupt
Capability
I/O Port 2
6 I/Os, with
Interrupt
Capability
POR/
Brownout
USART0
UART Mode
SPI Mode
I/O Port 3
8 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
TEST
Test
JTAG
Emulation
Module
8
6
8
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions, MSP430x11x2
TERMINAL
I/O
DESCRIPTION
NAME
DW & PW
RHB
I/O
DESCRIPTION
P1.0/TACLK/
ADC10CLK
13
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion
clock--10-bit ADC
P1.1/TA0
14
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0
output/BSL transmit
P1.2/TA1
15
23
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
16
24
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
17
25
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for
device programming and test
P1.5/TA0/TMS
18
26
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select,
input terminal for device programming and test
P1.6/TA1/TDI/TCLK
19
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input
terminal or test clock input
P1.7/TA2/TDO/TDI
20
28
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output
terminal or data input during programming
P2.0/ACLK/A0
8
6
I/O
General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0
P2.1/INCLK/A1
9
7
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit
ADC input A1
P2.2/TA0/A2
10
8
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0
output/analog input to 10-bit ADC input A2/BSL receive
P2.3/TA1/A3/V
REF-
/
V
eREF-
11
18
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1
output/analog input to 10-bit ADC input A3/negative reference voltage terminal.
P2.4/TA2/A4/V
REF+
/
V
eREF+
12
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit
ADC input A4/I/O of positive reference voltage terminal
P2.5/R
OSC
3
32
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO
nominal frequency
RST/NMI
7
5
I
Reset or nonmaskable interrupt input
TEST
1
29
I
Selects test mode for JTAG pins on P1.x
V
CC
2
30
Supply voltage
V
SS
4
1
Ground reference
XIN
6
3
I
Input terminal of crystal oscillator
XOUT
5
2
O
Output terminal of crystal oscillator
NC
NA
4,17,20,31
Not connected internally. Recommended connection to V
SS
.
Reserved
NA
9 - 16
Reserved pins. Recommended connection to V
SS
to avoid floating nodes, otherwise
increased current consumption may occur.
QFN Pad
NA
Package
Pad
QFN package pad connection to V
SS
recommended.
TDO or TDI is selected via JTAG instruction.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions, MSP430x12x2
TERMINAL
I/O
DESCRIPTION
NAME
DW & PW
RHB
I/O
DESCRIPTION
P1.0/TACLK/
ADC10CLK
21
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion
clock--10-bit ADC
P1.1/TA0
22
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0
output/BSL transmit
P1.2/TA1
23
23
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
24
24
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
25
25
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for
device programming and test
P1.5/TA0/TMS
26
26
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select,
input terminal for device programming and test
P1.6/TA1/TDI/TCLK
27
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input
terminal or test clock input
P1.7/TA2/TDO/TDI
28
28
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output
terminal or data input during programming
P2.0/ACLK/A0
8
6
I/O
General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0
P2.1/INCLK/A1
9
7
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit
ADC input A1
P2.2/TA0/A2
10
8
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0
output/analog input to 10-bit ADC input A2/BSL receive
P2.3/TA1/A3/V
REF-
/
V
eREF-
19
18
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1
output/analog input to 10-bit ADC input A3/negative reference voltage terminal.
P2.4/TA2/A4/V
REF+
/
V
eREF+
20
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit
ADC input A4/I/O of positive reference voltage terminal
P2.5/R
OSC
3
32
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO
nominal frequency
P3.0/STE0/A5
11
9
I/O
General-purpose digital I/O pin/slave transmit enable--USART0/SPI mode/analog
input to 10-bit ADC input A5
P3.1/SIMO0
12
10
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
13
11
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0
14
12
I/O
General-purpose digital I/O pin/external clock input--USART0/UART or SPI mode,
clock output--USART0/SPI mode clock input
P3.4/UTXD0
15
13
I/O
General-purpose digital I/O pin/transmit data out--USART0/UART mode
P3.5/URXD0
16
14
I/O
General-purpose digital I/O pin/receive data in--USART0/UART mode
P3.6/A6
17
15
I/O
General-purpose digital I/O pin/analog input to 10-bit ADC input A6
P3.7/A7
18
16
I/O
General-purpose digital I/O pin/analog input to 10-bit ADC input A7
RST/NMI
7
5
I
Reset or nonmaskable interrupt input
TEST
1
29
I
Selects test mode for JTAG pins on P1.x
V
CC
2
30
Supply voltage
V
SS
4
1
Ground reference
XIN
6
3
I
Input terminal of crystal oscillator
XOUT
5
2
O
Output terminal of crystal oscillator
NC
NA
4,17,20,31
Not connected internally. Recommended connection to V
SS
.
QFN Pad
NA
QFN package pad connection to V
SS
recommended.
TDO or TDI is selected via JTAG instruction.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
e.g. CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
e.g. JNE
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
OPERATION
Register
D D
MOV Rs,Rd
MOV R10,R11
R10 --> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)--> M(6+R6)
Symbolic (PC relative)
D D
MOV EDE,TONI
M(EDE) --> M(TONI)
Absolute
D D
MOV &MEM,&TCDAT
M(MEM) --> M(TCDAT)
Indirect
D
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) --> M(Tab+R6)
Indirect
autoincrement
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) --> R11
R10 + 2--> R10
Immediate
D
MOV #X,TONI
MOV #45,TONI
#45 --> M(TONI)
NOTE: S = source D = destination
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode AM;
-
All clocks are active
D
Low-power mode 0 (LPM0);
-
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
Low-power mode 1 (LPM1);
-
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO's dc-generator is disabled if DCO not used in active mode
D
Low-power mode 2 (LPM2);
-
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator remains enabled
ACLK remains active
D
Low-power mode 3 (LPM3);
-
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
ACLK remains active
D
Low-power mode 4 (LPM4);
-
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
Crystal oscillator is stopped
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh-0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash memory
WDTIFG
(see Note1)
KEYV (see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 4)
OFIFG (see Notes 1 and 4)
ACCVIFG (see Notes 1 and 4)
(Non)-maskable
(Non)-maskable
(Non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFF2h
9
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)
Maskable
0FFF0h
8
USART0 receive (see Note 5)
URXIFG0
Maskable
0FFEEh
7
USART0 transmit (see Note 5)
UTXIFG0
Maskable
0FFECh
6
ADC10
ADC10IFG
Maskable
0FFEAh
5
0FFE8h
4
I/O Port P2
(eight flags - see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE6h
3
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0-5) are implemented on the '11x2 and '12x2 devices.
4. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. USART0 is implemented in MSP430x12x2 devices only.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
6
5
4
0
OFIE
WDTIE
3
2
1
rw-0
rw-0
rw-0
Address
0h
NMIIE
ACCVIE
rw-0
WDTIE: Watchdog
Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE:
Oscillator fault enable
NMIIE:
(Non)maskable interrupt enable
ACCVIE:
Flash access violation interrupt enable
7
6
5
4
0
3
2
1
Address
01h
UTXIE0
URXIE0
rw-0
rw-0
URXIE0: USART0: UART and SPI receive-interrupt enable (MSP430x12x2 devices only)
UTXIE0: USART0: UART and SPI transmit-interrupt enable (MSP430x12x2 devices only)
interrupt flag register 1 and 2
7
6
5
4
0
OFIFG
WDTIFG
3
2
1
rw-0
rw-1
rw-(0)
Address
02h
NMIIFG
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI-pin
7
6
5
4
0
3
2
1
Address
03h
UTXIFG0
URXIFG0
rw-0
rw-1
URXIFG0: USART0: UART and SPI receive flag (MSP430x12x2 devices only)
UTXIFG0: USART0: UART and SPI transmit flag (MSP430x12x2 devices only)
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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POST OFFICE BOX 655303
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module enable registers 1 and 2
7
6
5
4
0
3
2
1
Address
04h
7
6
5
4
0
3
2
1
Address
05h
UTXE0
URXE0
USPIE0
rw-0
rw-0
URXE0:
USART0: UART mode receive enable (MSP430x12x2 devices only)
UTXE0:
USART0: UART mode transmit enable (MSP430x12x2 devices only)
USPIE0:
USART0: SPI mode transmit and receive enable (MSP430x12x2 devices only)
Legend
rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC
SFR bit is not present in device.
Bit can be read and written. It is Reset or Set by POR
rw-(0,1):
memory organization
MSP430F1122
MSP430F1132
MSP430F1222
MSP430F1232
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
4KB Flash
0FFFFh-0FFE0h
0FFFFh-0F000h
8KB Flash
0FFFFh-0FFE0h
0FFFFh-0E000h
4KB Flash
0FFFFh-0FFE0h
0FFFFh-0F000h
8KB Flash
0FFFFh-0FFE0h
0FFFFh-0E000h
Information memory
Size
Flash
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
Boot memory
Size
ROM
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
RAM
Size
256 Byte
02FFh - 0200h
256 Byte
02FFh - 0200h
256 Byte
02FFh - 0200h
256 Byte
02FFh - 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
MSP430x11x2
DW & PW Package
(20 Pins)
MSP430x12x2
DW & PW Package
(28 Pins)
MSP430x11x2/12x2
RHB Package
(32 Pins)
Data Transmit
14 - P1.1
22 - P1.1
22 - P1.1
Data Receive
10 - P2.2
10 - P2.2
8 - P2.2
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
D
Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment0 w/
Interrupt Vectors
0FFFFh
0FE00h
Information Memory
Flash Main Memory
Segment1
Segment2
Segment3
Segment4
Segment14
Segment15
SegmentA
SegmentB
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0F800h
0F7FFh
0F600h
0E3FFh
0E200h
0E1FFh
0E000h
010FFh
01080h
0107Fh
01000h
NOTE: All segments not implemented on all devices.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number
SLAU049.
oscillator and system clock
The clock system in the MSP430x11x2 and MSP430x12x2 devices is supported by the basic clock module that
includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a
high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes
in less than 6
s. The basic clock module provides the following clock signals:
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D
Main clock (MCLK), the system clock used by the CPU.
D
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are 3 8-bit I/O ports implemented--ports P1, P2, and P3 (only six port P2 I/O signals are available on
external pins; port P3 is implemented only on 'x12x2 devices):
D
All individual I/O bits are independently programmable.
D
Any combination of input, output, and interrupt conditions is possible.
D
Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2.
D
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins, but all control and data bits for port
P2 are implemented. Port P3 has no interrupt capability. Port P3 is implemented in MSP430x12x2
only.
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0 (MSP430x12x2 Only)
The MSP430x12x2 devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Output Pin Number
DW and PW
RHB
Device Input
Module
Module
Module Output
DW and PW
RHB
'11x2
20-Pin
'12x2
28-Pin
'11x2/12x2
32-Pin
Device Input
Signal
Module
Input Name
Module
Block
Module Output
Signal
'11x2
20-Pin
'12x2
28-Pin
'11x2/12x2
32-Pin
13 - P1.0
21 - P1.0
21 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
9 - P2.1
9 - P2.1
7 - P2.1
INCLK
INCLK
14 - P1.1
22 - P1.1
22 - P1.1
TA0
CCI0A
14 - P1.1
22 - P1.1
22 - P1.1
10 - P2.2
10 - P2.2
8 - P2.2
TA0
CCI0B
18 - P1.5
26 - P1.5
26 - P1.5
DV
SS
GND
CCR0
TA0
10 - P2.2
10 - P2.2
8 - P2.2
DV
CC
V
CC
ADC10 Internal
15 - P1.2
23 - P1.2
23 - P1.2
TA1
CCI1A
15 - P1.2
23 - P1.2
23 - P1.2
11 - P2.3
19 - P2.3
18 - P2.3
TA1
CCI1B
19 - P1.6
27 - P1.6
27 - P1.6
DV
SS
GND
CCR1
TA1
11 - P2.3
19 - P2.3
18 - P2.3
DV
CC
V
CC
ADC10 Internal
16 - P1.3
24 - P1.3
24 - P1.3
TA2
CCI2A
16 - P1.3
24 - P1.3
24 - P1.3
ACLK (internal)
CCI2B
20 - P1.7
28 - P1.7
28 - P1.7
DV
SS
GND
CCR2
TA2
12 - P2.4
20 - P2.4
19 - P2.4
DV
CC
V
CC
ADC10 Internal
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
ADC10
ADC data transfer start address
ADC memory
ADC control register 1
ADC10SA
ADC10MEM
ADC10CTL1
1BCh
1B4h
1B2h
ADC control register 0
ADC analog enable
ADC data transfer control register 1
ADC data transfer control register 0
ADC10CTL0
ADC10AE
ADC10DTC1
ADC10DTC0
1B0h
04Ah
049h
048h
Timer_A
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
USART0
(in MSP430x12x2 only)
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
077h
076h
075h
074h
073h
072h
071h
070h
Basic Clock
Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
Port P2
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P3
(in MSP430x12x2 only)
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3SEL
P3DIR
P3OUT
P3IN
01Bh
01Ah
019h
018h
Special Function
Module enable2
Module enable1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME2
ME1
IFG2
IFG1
IE2
IE1
005h
004h
003h
002h
001h
000h
absolute maximum ratings
Voltage applied at V
CC
to V
SS
-0.3 V to 4.1 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note)
-0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal
2 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
(unprogrammed device)
-55
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
(programmed device)
-40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
SS
. The JTAG fuse-blow voltage, V
FB
, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution, V
CC
(see Note 1)
MSP430F11x2
1.8
3.6
V
Supply voltage during program/erase flash memory, V
CC
MSP430F11x2
MSP430F12x2
2.7
3.6
V
Supply voltage, V
SS
0
V
Operating free-air temperature range, T
A
MSP430F11x2
MSP430F12x2
-40
85
C
LF mode selected, XTS=0
Watch crystal
32 768
Hz
LFXT1 crystal frequency, f
(LFXT1)
Ceramic resonator
450
8000
(see Note 1 & Note 2)
XT1 selected mode, XTS=1
Crystal
1000
8000
kHz
V
CC
= 1.8 V,
MSP430F11x2
MSP430F12x2
dc
4.15
Processor frequency f
(system)
(MCLK signal)
V
CC
= 3.6 V,
MSP430F11x2
MSP430F12x2
dc
8
MHz
NOTES:
1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 M
from XOUT to V
SS
when V
CC
<2.5 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at V
CC
2.2 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at V
CC
2.8 V.
2. The LFXT1 oscillator in LF-mode requires a watch crystal.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
1.8 V
3.6 V
2.7 V 3 V
4.15 MHz
8.0 MHz
Supply Voltage - V
Supply voltage range, 'F11x2/12x2,
during flash memory programming
Supply voltage range,
'F11x2/12x2, during
program execution
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum V
CC
of 2.7 V.
f
(system)
(MHz)
Figure 1. Frequency vs Supply Voltage
supply current (into V
CC
) excluding external current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
A
= -40
C +85
C,
f
= f
= 1
MHz,
V
CC
= 2.2 V
200
250
I
(AM)
Active mode
f
MCLK
= f
(SMCLK)
= 1
MHz,
f(ACLK)
= 32,768 Hz,
Program executes in Flash
V
CC
= 3 V
300
350
A
I
(AM)
Active mode
T
A
= -40
C +85
C,
V
CC
= 2.2 V
3
5
f
(MCLK)
= f
(SMCLK)
=
f
(ACLK)
= 4096 Hz,
Program executes in Flash
V
CC
= 3 V
11
18
A
T
A
= -40
C +85
C,
V
CC
= 2.2 V
32
45
I
(CPUOff)
Low-power mode, (LPM0)
f
(MCLK)
= 0, f
(SMCLK)
= 1
MHz,
f(ACLK)
= 32,768 Hz
V
CC
= 3 V
55
70
A
T
A
= -40
C +85
C,
V
CC
= 2.2 V
11
14
I
(LPM2)
Low-power mode, (LPM2)
f
(MCLK)
= f
(SMCLK)
= 0
MHz,
f(ACLK)
= 32,768 Hz, SCG0 = 0
V
CC
= 3 V
17
22
A
T
A
= -40
C
0.8
1.2
T
A
= 25
C
V
CC
= 2.2 V
0.7
1
A
T
A
= 85
C
CC
1.6
2.3
I
(LPM3)
Low-power mode, (LPM3)
T
A
= -40
C
1.8
2.2
T
A
= 25
C
V
CC
= 3 V
1.6
1.9
A
T
A
= 85
C
CC
2.3
3.4
T
A
= -40
C
0.1
0.5
I
(LPM4)
Low-power mode, (LPM4)
T
A
= 25
C
V
CC
= 2.2 V/3 V
0.1
0.5
A
(LPM4)
T
A
= 85
C
CC
0.8
1.9
NOTES:
1. All inputs are tied to 0 V or V
CC
. Outputs do not source or sink any current.
current consumption of active mode versus system frequency
I
AM
= I
AM[1 MHz]
f
system
[MHz]
current consumption of active mode versus supply voltage
I
AM
= I
AM[3 V]
+ 120
A/V
(V
CC
-3 V)
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
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POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
= 2.2 V
1.1
1.5
V
IT+
Positive-going input threshold voltage
V
CC
= 3 V
1.5
1.9
V
V
CC
= 2.2 V
0.4
0.9
V
IT-
Negative-going input threshold voltage
V
CC
= 3 V
0.9
1.3
V
V
CC
= 2.2 V
0.3
1.1
V
hys
Input voltage hysteresis, (V
IT+
- V
IT-
)
V
CC
= 3 V
0.5
1
V
standard inputs - RST/NMI, TEST; JTAG: TCK, TMS, TDI/TCLK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IL
Low-level input voltage
V
SS
V
SS
+0.6
V
V
IH
High-level input voltage
V
CC
= 2.2 V / 3 V
0.8
V
CC
V
CC
V
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
2.2 V/3 V
1.5
cycle
t
(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, External trigger signal
2.2 V
62
(int)
for the interrupt flag, (see Note 1)
3 V
50
ns
2.2 V
62
t
(cap)
Timer_A, capture timing
TA0, TA1, TA2
3 V
50
ns
Timer_A clock frequency
2.2 V
8
f
(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK
t
(H)
= t
(L)
3 V
10
MHz
2.2 V
8
f
(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
trigger signals shorter than t
(int)
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
is measured in
MCLK cycles.
leakage current
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Port P1: P1.x, 0
7
(see Notes 1 and 2)
2.2 V/3 V
50
I
lkg(Px.x)
High-impedance leakage current
Port P2: P2.x, 0
5
(see Notes 1 and 2)
2.2 V/3 V
50
nA
NOTES:
1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
(OHmax)
= -1.5 mA
See Note 1
V
CC
-0.25
V
CC
I
(OHmax)
= -6 mA
V
CC
= 2.2 V
See Note 2
V
CC
-0.6
V
CC
V
OH
High-level output voltage
I
(OHmax)
= -1.5 mA
See Note 1
V
CC
-0.25
V
CC
V
I
(OHmax)
= -6 mA
V
CC
= 3 V
See Note 2
V
CC
-0.6
V
CC
I
(OLmax)
= 1.5 mA
See Note 1
V
SS
V
SS
+0.25
I
(OLmax)
= 6 mA
V
CC
= 2.2 V
See Note 2
V
SS
V
SS
+0.6
V
OL
Low-level output voltage
I
(OLmax)
= 1.5 mA
See Note 1
V
SS
V
SS
+0.25
V
I
(OLmax)
= 6 mA
V
CC
= 3 V
See Note 2
V
SS
V
SS
+0.6
NOTES:
1. The maximum total current, I
OHmax
and I
OLmax
, for all outputs combined, should not exceed
12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, I
OHmax
and I
OLmax
, for all outputs combined, should not exceed
48 mA to hold the maximum voltage
drop specified.
outputs P1.x, P2.x, P3.x, TAx
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
f
(P20)
P2.0/ACLK, C
L
= 20 pF
2.2 V/3 V
f
System
f
(TAx)
Output frequency
TA0, TA1, TA2, C
L
= 20 pF,
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V
dc
f
System
MHz
f
SMCLK
= f
LFXT1
= f
XT1
40%
60%
f
SMCLK
= f
LFXT1
= f
LF
35%
65%
P1.4/SMCLK,
C
L
= 20 pF
f
SMCLK
= f
LFXT1/n
2.2 V/3 V
50%-
15 ns
50%
50%+
15 ns
t
(Xdc)
Duty cycle of O/P
frequency
f
SMCLK
= f
DCOCLK
2.2 V/3 V
50%-
15 ns
50%
50%+
15 ns
frequency
f
P20
= f
LFXT1
= f
XT1
40%
60%
P2.0/ACLK,
f
P20
= f
LFXT1
= f
LF
2.2 V/3 V
30%
70%
C
L
= 20 pF
f
P20
= f
LFXT1/n
50%
t
(TAdc)
TA0, TA1, TA2,
C
L
= 20 pF, Duty cycle = 50%
2.2 V/3 V
0
50
ns
NOTES:
1. The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, and P3 (see Note)
Figure 2
V
OL
- Low-Level Output Voltage - V
0
4
8
12
16
20
24
28
32
0.0
0.5
1.0
1.5
2.0
2.5
V
CC
= 2.2 V
P1.0
T
A
= 25
C
T
A
= 85
C
OLI
-

T
ypical Low-Level Output Current
-
mA
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
Figure 3
V
OL
- Low-Level Output Voltage - V
0
10
20
30
40
50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
CC
= 3 V
P1.0
T
A
= 25
C
T
A
= 85
C
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
OLI
-

T
ypical Low-Level Output Current
-
mA
Figure 4
V
OH
- High-Level Output Voltage - V
-28
-24
-20
-16
-12
-8
-4
0
0.0
0.5
1.0
1.5
2.0
2.5
V
CC
= 2.2 V
P1.0
T
A
= 25
C
T
A
= 85
C
OHI
-

T
ypical High-Level Output Current
-
mA
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
Figure 5
V
OH
- High-Level Output Voltage - V
-60
-50
-40
-30
-20
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
CC
= 3 V
P1.0
T
A
= 25
C
T
A
= 85
C
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
OHI
-

T
ypical High-Level Output Current
-
mA
NOTE:
Only one output is loaded at a time.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
(LPM0)
V
CC
= 2.2 V/3 V
100
t
(LPM2)
V
CC
= 2.2 V/3 V
100
ns
f
(MCLK)
= 1 MHz,
V
CC
= 2.2 V/3 V
6
t
(LPM3)
f
(MCLK)
= 2 MHz,
V
CC
= 2.2 V/3 V
6
s
(LPM3)
Delay time (see Note 1)
f
(MCLK)
= 3 MHz,
V
CC
= 2.2 V/3 V
6
f
(MCLK)
= 1 MHz,
V
CC
= 2.2 V/3 V
6
t
(LPM4)
f
(MCLK)
= 2 MHz,
V
CC
= 2.2 V/3 V
6
s
(LPM4)
f
(MCLK)
= 3 MHz,
V
CC
= 2.2 V/3 V
6
NOTES:
1. Parameter applicable only if DCOCLK is used for MCLK.
USART (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
= 2.2 V
200
430
800
t
(
)
USART: deglitch time
V
CC
= 3 V
150
280
500
ns
NOTES:
1. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t
(
)
to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t
(
)
. The operating conditions
to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on
the URXD line.
RAM
PARAMETER
MIN
NOM
MAX
UNIT
V
(RAMh)
CPU halted (see Note 1)
1.6
V
NOTES:
1. This parameter defines the minimum supply voltage V
CC
when the data in the program memory RAM remains unchanged. No
program execution should happen during this supply voltage condition.
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
d(BOR)
2000
s
V
CC(start)
dV
CC
/dt
3 V/s
0.7
V
(B_IT-)
V
V
(B_IT-)
dV
CC
/dt
3 V/s
1.71
V
V
hys(B_IT-)
Brownout
dV
CC
/dt
3 V/s
70
130
180
mV
t
(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
V
CC
= 2.2 V/3 V
2
s
NOTES:
1. The current consumption of the brown-out module is already included in the I
CC
current consumption data.
2. During power up, the CPU begins code execution following a period of t
d(BOR)
after V
CC
= V
(B_IT-)
+ V
hys(B_IT-)
.
The default DCO settings must not be changed until V
CC
V
CC(min)
, where V
CC(min)
is the minimum supply voltage for the
desired operating frequency. See the MSP430x1xx Family User's Guide for more information on the brownout circuit.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0
1
td(BOR)
VCC
V(B_IT-)
Vhys(B_IT-)
V
CC(start)
Set signal for
POR circuitry
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
VCC(min)
VCC
3 V
t pw
0
0.50
1
1.50
2
0.001
1
1000
V = 3.0 V
Typical Conditions
1ns
1ns
t
pw
- Pulse Width -
s
V
CC(min)
-
V
t
pw
- Pulse Width -
s
cc
Figure 7. V
CC(min)
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
0
0.50
1
1.50
2
VCC(min)
t pw
t
pw
- Pulse Width -
s
V
CC(min)
-
V
3 V
0.001
1
1000
t
fall
t
rise
t
pw
- Pulse Width -
s
t
fall
= t
rise
V = 3.0 V
Typical Conditions
cc
Figure 8. V
CC(min)
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
2.2 V
0.08
0.12
0.15
f
(DCO03)
R
sel
= 0, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
0.08
0.13
0.16
MHz
2.2 V
0.14
0.19
0.23
f
(DCO13)
R
sel
= 1, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
0.14
0.18
0.22
MHz
2.2 V
0.22
0.3
0.36
f
(DCO23)
R
sel
= 2, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
0.22
0.28
0.34
MHz
2.2 V
0.37
0.49
0.59
f
(DCO33)
R
sel
= 3, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
0.37
0.47
0.56
MHz
2.2 V
0.61
0.77
0.93
f
(DCO43)
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
0.61
0.75
0.9
MHz
2.2 V
1
1.2
1.5
f
(DCO53)
R
sel
= 5, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
1
1.3
1.5
MHz
2.2 V
1.6
1.9
2.2
f
(DCO63)
R
sel
= 6, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
1.69
2
2.29
MHz
2.2 V
2.4
2.9
3.4
f
(DCO73)
R
sel
= 7, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
2.7
3.2
3.65
MHz
2.2 V
4
4.5
4.9
f
(DCO77)
R
sel
= 7, DCO = 7, MOD = 0, DCOR = 0, T
A
= 25
C
3 V
4.4
4.9
5.4
MHz
f
DCO40
f
DCO40
f
DCO40
f
(DCO47)
R
sel
= 4, DCO = 7, MOD = 0, DCOR = 0, T
A
= 25
C
2.2 V/3 V
f
DCO40
x1.7
f
DCO40
x2.1
f
DCO40
x2.5
MHz
S
(Rsel)
S
R
= f
Rsel+1
/f
Rsel
2.2 V/3 V
1.35
1.65
2
S
(DCO)
S
DCO
= f
DCO+1
/f
DCO
2.2 V/3 V
1.07
1.12
1.16
ratio
2.2 V
-0.31
-0.36
-0.4
D
t
Temperature drift, R
sel
= 4, DCO = 3, MOD = 0 (see Note 1)
3 V
-0.33
-0.38
-0.43
%/
C
D
V
Drift with V
CC
variation, R
sel
= 4, DCO = 3, MOD = 0
(see Note 1)
2.2 V/3 V
5
%/V
NOTES:
1. These parameters are not production tested.
2.2 V
3 V
V
CC
Max
Min
Max
Min
f
(DCOx7)
f
(DCOx0)
Frequency V
ariance
0
1
2
3
4
5
6
7
DCO Steps
1
f DCOCLK
Figure 9. DCO Characteristics
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
f
(
DCOx0)
to f
(
DCOx7)
are valid for all devices.
D
All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D
DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S
DCO
.
D
Modulation control bits MOD0 to MOD4 select how often f
(
DCO+1)
is used within the period of 32 DCOCLK
cycles. The frequency f
(DCO)
is used for the remaining cycles. The frequency is an average equal to:
f
average
+
32 f
(DCO)
f
(DCO)1)
MOD f
(DCO)
)(32*MOD) f
(DCO)1)
DCO when using R
OSC
(see Note 1)
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1,
2.2 V
1.8
15%
MHz
f
DCO
, DCO output frequency
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1,
T
A
= 25
C
3 V
1.95
15%
MHz
D
t
, Temperature drift
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
0.1
%/
C
D
v
, Drift with V
CC
variation
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
10
%/V
NOTES:
1. R
OSC
= 100k
. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T
K
=
50ppm/
C.
crystal oscillator,LFXT1
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Pin load
XTS=0; LF mode selected
2.2 V / 3 V
12
C
XIN
Pin load
capacitance
XTS=1; XT1 mode selected (see Note 1)
2.2 V / 3 V
2
pF
Pin load
XTS=0; LF mode selected
2.2 V / 3 V
12
C
XOUT
Pin load
capacitance
XTS=1; XT1 mode selected (see Note 1)
2.2 V / 3 V
2
pF
V
IL
V
SS
0.2
V
CC
V
V
IH
Input levels at XIN
see Note 2
2.2 V / 3 V
0.8
V
CC
V
CC
V
NOTES:
1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V
CC
Analog supply voltage
V
SS
= 0 V
2.2
3.6
V
V
(P6.x/Ax)
Analog input voltage
range (see Note 2)
All Ax terminals. Analog inputs
selected in ADC10AE register and PxSel.x=1
V
SS
V
Px.x/Ax
V
CC
0
V
CC
V
Operating supply current
f
ADC10CLK
= 5.0 MHz
ADC10ON = 1, REFON = 0
V
CC
= 2.2 V
0.52
1.05
I
ADC10
into V
CC
terminal
(see Note 3)
ADC10ON = 1, REFON = 0
ADC10SHT0=1, ADC10SHT1=0,
ADC10DIV=0
V
CC
= 3 V
0.6
1.2
mA
I
REF+
Reference operating
supply current,
reference buffer disabled
(see Note 4)
f
ADC10CLK
= 5.0 MHz
ADC10ON = 0,
REFON = 1, REF2_5V = x;
REFOUT = 0
V
CC
=
2.2V/3 V
0.25
0.4
mA
Reference buffer
f
ADC10CLK
= 5.0 MHz
ADC10ON = 0,
ADC10SR = 0
1.1
1.4
I
REFB
operating supply current
(see Note 4)
ADC10ON = 0,
REFON = 1, REF2_5V = 0
REFOUT = 1
ADC10SR = 1
0.46
0.55
mA
C
I
Input capacitance
Only one terminal can be selected
at one time, Px.x/Ax
V
CC
= 2.2 V
27
pF
R
I
Input MUX ON resistance
0V
V
Ax
V
CC
V
CC
= 3 V
2000
Not production tested, limits verified by design
NOTES:
1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V
R+
to V
R-
for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter I
ADC10
.
4. The internal reference current is supplied via terminal V
CC
. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
10-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
V
eREF+
Positive external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 2)
1.4
V
CC
V
V
REF- /
V
eREF-
Negative external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 3)
0
1.2
V
(V
eREF+
-
V
REF-/
V
eREF-
)
Differential external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 4)
1.4
V
CC
V
I
VeREF+
Static input current
0V
V
eREF+
V
CC
2.2 V/3 V
1
A
I
VREF-/VeREF-
Static input current
0V
V
eREF-
V
CC
2.2 V/3 V
1
A
NOTES:
1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C
I
, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Positive built-in reference
REF2_5V = 1 for 2.5 V
I
VREF+
I
VREF+
max
V
CC
= 3 V
2.35
2.5
2.65
V
REF+
Positive built-in reference
voltage output
REF2_5V = 0 for 1.5 V
I
VREF+
I
VREF+
max
V
CC
=
2.2 V/3 V
1.41
1.5
1.59
V
REF2_5V = 0, I
VREF+
1mA
2.2
V
CC(min)
V
CC
minimum voltage,
Positive built-in reference
REF2_5V = 1, I
VREF+
0.5mA
V
REF+
+ 0.15
V
V
CC(min)
Positive built-in reference
active
REF2_5V = 1, I
VREF+
1mA
V
REF+
+ 0.15
V
Load current out of V
REF+
V
CC
= 2.2 V
0.5
I
VREF+
Load current out of V
REF+
terminal
V
CC
= 3 V
1
mA
I
VREF+
= 500
A +/- 100
A
V
CC
= 2.2 V
2
Load-current regulation
Analog input voltage ~0.75 V;
REF2_5V = 0
V
CC
= 3 V
2
LSB
I
L(VREF)+
Load-current regulation
V
REF+
terminal
I
VREF+
= 500
A
100
A
Analog input voltage ~1.25 V;
REF2_5V = 1
V
CC
= 3 V
2
LSB
Load current regulation
I
VREF+
=100
A
900
A,
ADC10SR = 0
400
t
DL(VREF) +
Load current regulation
V
REF+
terminal
V
CC
=3 V, Ax ~0.5 x V
REF+
Error of conversion result
1 LSB
ADC10SR = 1
2000
ns
C
VREF+
Capacitance at pin V
REF+
(see Note 1)
REFON =1, I
VREF+
1 mA
V
CC
=
2.2 V/3 V
100
pF
T
REF+
Temperature coefficient of
built-in reference
I
VREF+
is a constant in the range of
0 mA
I
VREF+
1 mA
V
CC
=
2.2 V/3 V
100
ppm/
C
Settle time of internal
I
VREF+
= 0.5 mA,V
REF+
= 1.5 V, V
CC
= 3.6 V,
REFON = 0
1
30
t
REFON
reference voltage and
V
REF+
I
VREF+
= 0.5 mA, V
REF+
= 1.5 V,
ADC10SR = 0
0.8
s
V
REF+
(see Note 2)
I
VREF+
= 0.5 mA, V
REF+
= 1.5 V,
V
CC
= 2.2 V, REFON = 1
ADC10SR = 1
2.5
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V
REF+
/V
eREF+
(REFOUT=1),
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after t
REFON
is less than
0.5 LSB.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
For specified performance of
ADC10SR = 0
0.450
6.3
f
ADC10CLK
For specified performance of
ADC10 linearity parameters
ADC10SR = 1
0.450
1.5
MHz
f
ADC10OSC
ADC10DIV=0,
f
ADC10CLK
=f
ADC10OSC
V
CC
=
2.2 V/ 3V
3.7
6.3
MHz
t
Conversion time
Internal oscillator,
f
ADC10OSC
= 3.7 MHz to
6.3 MHz
V
CC
=
2.2 V/ 3 V
2.06
3.51
s
t
CONVERT
Conversion time
External f
ADC10CLK
from ACLK, MCLK or SMCLK:
ADC10SSEL
0
13
ADC10DIV
1/f
ADC10CLK
s
t
ADC10ON
Turn on settling time of
the ADC
(see Note 1)
100
ns
R
S
= 400
, R
I
= 2000
,
V
CC
= 3 V
1400
t
Sample
Sampling time
R
S
= 400
, R
I
= 2000
,
C
I
= 20 pF (see Note 2)
V
CC
= 2.2 V
1400
ns
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The condition is that the error in a conversion started after t
ADC10ON
is less than
0.5 LSB. The reference and input signal are already
settled.
2. Approximately eight Tau (
) are needed to get an error of less than
0.5 LSB.
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, R
S
= external source resistance)
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 2.5
s. (ADC10SR = 1, n = ADC resolution = 10, R
S
= external source resistance)
10-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
1.4 V
(V
eREF+
- V
REF-
/V
eREF-
) min
1.6 V
1
E
I
Integral linearity error
1.6 V < (V
eREF+
- V
REF-
/V
eREF-
) min
[V
CC
]
2.2 V/3 V
1
LSB
E
D
Differential linearity
error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
)
2.2 V/3 V
1
LSB
E
O
Offset error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
Internal impedance of source R
S
< 100
,
2.2 V/3 V
2
4
LSB
E
G
Gain error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
2.2 V/3 V
1.1
2
LSB
E
T
Total unadjusted
error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
2.2 V/3 V
2
5
LSB
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
10-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
Operating supply current into
REFON = 0, INCH = 0Ah,
2.2 V
40
120
I
SENSOR
Operating supply current into
V
CC
terminal (see Note 1)
REFON = 0, INCH = 0Ah,
ADC10ON=NA, T
A
= 25
_
C
3 V
60
160
A
ADC10ON = 1, INCH = 0Ah,
2.2 V
986
986
5%
V
SENSOR
ADC10ON = 1, INCH = 0Ah,
T
A
= 0
C
3 V
986
986
5%
mV
2.2 V
3.55
3.55
3%
TC
SENSOR
ADC10ON = 1, INCH = 0Ah
3 V
3.55
3.55
3%
mV/
C
Sample time required if channel
ADC10ON = 1, INCH = 0Ah,
2.2 V
30
t
SENSOR(sample)
Sample time required if channel
10 is selected (see Note 2)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result
1 LSB
3 V
30
s
Current into divider at channel 11
2.2 V
NA
I
VMID
Current into divider at channel 11
(see Note 3)
ADC10ON = 1, INCH = 0Bh,
3 V
NA
A
ADC10ON = 1, INCH = 0Bh,
2.2 V
1.1
1.1
0.04
V
MID
V
CC
divider at channel 11
ADC10ON = 1, INCH = 0Bh,
V
MID
is ~0.5 x V
CC
3 V
1.5
1.50
0.04
V
Sample time required if channel
ADC10ON = 1, INCH = 0Bh,
2.2 V
1400
t
VMID(sample)
Sample time required if channel
11 is selected (see Note 4)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result
1 LSB
3 V
1220
ns
Not production tested, limits characterized
NOTES:
1. The sensor current I
SENSOR
is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the
temperature sensor input (INCH = 0Ah).
2. The typical equivalent impedance of the sensor is 51 k
. The sample time required includes the sensor-on time t
SENSOR(on)
.
3. No additional current is needed. The V
MID
is used during sampling.
4. The on-time t
VMID(on)
is included in the sampling time t
VMID(sample)
; no additional on time is needed.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
2.7
3.6
V
f
FTG
Flash Timing Generator frequency
257
476
kHz
I
PGM
Supply current from V
CC
during program
2.7 V/ 3.6 V
3
5
mA
I
ERASE
Supply current from V
CC
during erase
2.7 V/ 3.6 V
3
7
mA
t
CPT
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
t
CMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
200
ms
Program/Erase endurance
10
4
10
5
cycles
t
Retention
Data retention duration
T
J
= 25
C
100
years
t
Word
Word or byte program time
35
t
Block, 0
Block program time for 1
st
byte or word
30
t
Block, 1-63
Block program time for each additional byte or word
21
t
Block, End
Block program end-sequence wait time
see Note 3
6
t
FTG
t
Mass Erase
Mass erase time
5297
t
Seg Erase
Segment erase time
4819
NOTES:
1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
FTG
,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller's state machine; t
FTG
= 1/f
FTG
.
JTAG Interface
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
2.2 V
0
5
MHz
f
TCK
TCK input frequency
see Note 1
3 V
0
10
MHz
R
Internal
Internal pull-down resistance on TEST
see Note 2
2.2 V/ 3 V
25
60
90
k
NOTES:
1. f
TCK
may be restricted to meet the timing requirements of the module selected.
2. TEST pull-down resistor implemented in all Flash versions.
JTAG Fuse (see Note 1)
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
V
CC(FB)
Supply voltage during fuse-blow condition
T
A
= 25
C
2.5
V
V
FB
Voltage level on TEST for fuse-blow
6
7
V
I
FB
Supply current into TEST during fuse blow
100
mA
t
FB
Time to blow fuse
1
ms
NOTES:
1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
EN
D
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P1IE.x
P1IFG.x
P1IRQ.x
Interrupt
Flag
P1IES.x
P1SEL.x
Module X IN
P1IN.x
P1OUT.x
Module X OUT
Direction Control
From Module
P1DIR.x
P1SEL.x
Pad Logic
NOTE: x = Bit/identifier, 0 to 3 for port P1
PnSel.x
PnDIR.x
DIRECTION
CONTROL FROM
MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
ADC10CLK
P1IN.0
TACLK
P1IE.0
P1IFG.0
P1IES.0
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
Out0 signal
P1IN.1
CCI0A
P1IE.1
P1IFG.1
P1IES.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 signal
P1IN.2
CCI1A
P1IE.2
P1IFG.2
P1IES.2
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal
P1IN.3
CCI2A
P1IE.3
P1IFG.3
P1IES.3
Signal from or to Timer_A
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
EN
D
P1.4-P1.7
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P1IE.x
P1IFG.x
P1IRQ.x
Interrupt
Flag
P1IES.x
P1SEL.x
Module X IN
P1IN.x
P1OUT.x
Module X OUT
Direction Control
From Module
P1DIR.x
P1SEL.x
Pad Logic
Bus Keeper
60 k
Control by
JTAG
0
1
TDO
Controlled By JTAG
P1.x
TDI
P1.x
TST
TMS
TST
TCK
TST
Controlled by JTAG
TST
P1.x
P1.x
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
Typical
TEST
Bum
and
Test Fuse
DV
CC
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
Out0 signal
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out1 signal
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
Signal from or to Timer_A
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2OUT.x
Module X Out
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x
P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x
EN
Set
Q
0
1
1
0
to ADC10,
P2.0/ACLK/A0
P2.1/INCLK/A1
P2.2/TA0/A2
Module X In
P2IN.x
a0, or a1, or a2
selected in
ADC10
Pad Logic
0: input
1: output
Bus
Keeper
ADC10AE.x
NOTE: 0
x
2
a0, or a1, or a2
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
unused
P2IE.0
P2IFG.0
P1IES.0
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
V
SS
P2IN.1
INCLK
P2IE.1
P2IFG.1
P1IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
OUT0 signal
P2IN.2
CCI0B
P2IE.2
P2IFG.2
P1IES.2
Timer_A
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2OUT.4
Module X Out
P2DIR.4
P2SEL.4
D
EN
Interrupt
Edge
Select
P2IES.4
P2SEL.4
P2IE.4
P2IFG.4
P2IRQ.07
EN
Set
Q
0
1
1
0
to ADC10, a4
P2.4/
Unused
P2IN.4
a4 Selected
Pad Logic
0: input
1: output
Bus
Keeper
ADC10AE.4
P2DIR.4
TA2/
A4/
V
REF+
P2OUT.3
Module X Out
P2DIR.3
P2SEL.3
D
EN
Interrupt
Edge
Select
P2IES.x
P2SEL.x
P2IE.4
P2IFG.4
P2IRQ.07
EN
Set
Q
0
1
1
0
to ADC10, a3
P2.3/
Module X In
P2IN.4
a3 Selected
Pad Logic
0: input
1: output
Bus
Keeper
ADC10AE.3
P2DIR.3
TA1/
A3/
VREF-
_
+
Reference Circuit
in ADC10 Module
ON
ON
Typ.
1.25 V
a10 on REFON
REF_x
AV
CC
OUT
REF+
2_5 V
AV
CC
V +
R
AV
SS
V -
R
0
1
SREF
ADC10
CTL0.12..14)
SREF.2
ADC10
CTL0.14)
0,4
1,5
0
/V eREF-
VeREF+
/
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger (continued)
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out1 signal
P2IN.3
CCI1B
P2IE.3
P2IFG.3
P1IES.3
P2Sel.4
P2DIR.4
P2DIR.4
P2OUT.4
Out2 signal
P2IN.4
Unused
P2IE.4
P2IFG.4
P1IES.4
Timer_A
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and R
OSC
function for the Basic Clock Module
EN
D
P2.5/R
OSC
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.5
P2IFG.5
P2IRQ.5
Interrupt
Flag
P2IES.5
P2SEL.5
Module X IN
P2IN.5
P2OUT.5
Module X OUT
Direction Control
From Module
P2DIR.5
P2SEL.5
Pad Logic
NOTE: DCOR: Control bit from Basic Clock Module: if it is set P2.5 is disconnected from P2.5 pad.
Bus Keeper
0
1
0
1
V
CC
Internal to
Basic Clock
Module
DCOR
DC
Generator
0: Input
1: Output
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
V
SS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded bits P2.6 and P2.7
EN
D
0
1
0
1
Interrupt
Edge
Select
EN
Set
Q
P2IE.x
P2IFG.x
P2IRQ.x
Interrupt
Flag
P2IES.x
P2SEL.x
Module X IN
P2IN.x
P2OUT.x
Module X OUT
Direction Control
From Module
P2DIR.x
P2SEL.x
Bus Keeper
0
1
0: Input
1: Output
Node Is Reset With PUC
PUC
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x
P2DIR.x
DIRECTION
CONTROL
FROM MODULE
P2OUT.x
MODULE X OUT
P2IN.x
MODULE X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
V
SS
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
V
SS
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0, P3.6 and P3.7 input/output with Schmitt-trigger
P3OUT.x
Module X Out
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
0
1
1
0
To ADC10
P3.0/STE0/A5
P3.6/A6
P3.7/A7
Module X In
P3IN.x
a5, or a6, or a7
selected in
ADC10
Pad Logic
0: input
1: output
Bus
Keeper
ADC10AE.x
NOTE: x (0,6,7)
a5, or a6, or a7
PnSel.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P3Sel.0
P3DIR.0
V
SS
P3OUT.0
V
SS
P3IN.0
STE0
P3Sel.6
P3DIR.1
P3DIR.6
P3OUT.6
V
SS
P3IN.6
Unused
P3Sel.7
P3DIR.2
P3DIR.7
P3OUT.7
V
SS
P3IN.7
Unused
USART0
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.1 input/output with Schmitt-trigger
P3.1/SIMO0
P3IN.1
Pad Logic
EN
D
P3OUT1
P3DIR.1
P3SEL.1
(SI)MO0
0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
From USART0
SI(MO)0
To USART0
0: Input
1: Output
port P3, P3.2, input/output with Schmitt-trigger
P3.2/SOMI0
P3IN.2
Pad Logic
EN
D
P3OUT.2
P3DIR.2
P3SEL.2
0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)0
From USART0
(SO)MI0
To USART0
0: Input
1: Output
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.3, input/output with Schmitt-trigger
P3.3/UCLK0
P3IN.3
Pad Logic
EN
D
P3OUT.3
P3DIR.3
P3SEL.3
UCLK.0
0
1
0
1
DCM_UCLK
SYNC
MM
STE
STC
From USART0
UCLK0
To USART0
0: Input
1: Output
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode:
The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
port P3, P3.4, and P3.5 input/output with Schmitt-trigger
P3IN.x
Module X IN
Pad Logic
EN
D
P3OUT.x
P3DIR.x
P3SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
P3.4/UTXD0
P3.5/URXD0
0: Input
1: Output
x {4,5}
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P3Sel.4
P3DIR.4
V
CC
P3OUT.4
UTXD0
P3IN.4
Unused
P3Sel.5
P3DIR.5
V
SS
P3OUT.5
V
SS
P3IN.5
URXD0
Output from USART0 module
Input to USART0 module
MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D - JANUARY 2002 - REVISED AUGUST 2004
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I
TF
, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 10). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 10. Fuse Check Mode Current, MSP430F11x2, MSP430F12x2
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
MSP430A004IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430A004IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430A005IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430A005IPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1122IDW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1122IDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1122IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1122IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1122IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1122IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1132IDW
ACTIVE
SOIC
DW
20
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1YEAR/
Level-1-220C-UNLIM
MSP430F1132IDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1132IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1132IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1132IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1132IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1222IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1222IDWR
ACTIVE
SOIC
DW
28
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1222IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1222IPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1222IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1222IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1232IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1232IDWR
ACTIVE
SOIC
DW
28
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1232IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
MSP430F1232IPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F1232IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F1232IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
Addendum-Page 2
MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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