Document Outline
- SLAS368D - MSP430x15x
- features
- description
- pin designation, MSP430F155, MSP430F156, and MSP430F157
- pin designation, MSP430F167, MSP430F168, MSP430F169
- pin designation, MSP430F1610, MSP430F1611, MSP430F1612
- functional block diagrams
- MSP430x15x
- MSP430x16x
- MSP430x161x
- Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization (MSP430F15x)
- memory organization (MSP430F16x)
- memory organization (MSP430F161x)
- bootstrap loader (BSL)
- flash memory
- peripherals
- DMA controller
- oscillator and system clock
- brownout, supply voltage supervisor
- digital I/O
- watchdog timer
- hardware multiplier (MSP430x16x/161x Only)
- USART0
- USART1 (MSP430x16x/161x Only)
- timer_A3
- timer_B3 (MSP430x15x Only)
- timer_B7 (MSP430x16x/161x Only)
- comparator_A
- ADC12
- DAC12
- peripheral file map
- absolute maximum ratings over operating free-air temperature (unless otherwise noted)
- recommended operating conditions
- electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
- MSP430F15x/16x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC)
- MSP430F161x supply current into AVCC + DVCC excluding external current (AVCC = DVCC = VCC)
- SCHMITT-trigger inputs - Ports P1, P2, P3, P4, P5, P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx, TBx
- leakage current - Ports P1, P2, P3, P4, P5 and P6 (see Note 1)
- outputs - Ports P1, P2, P3, P4, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- Comparator_A (see Note 1)
- POR/brownout reset (BOR) (see Notes 1 and 2)
- typical characteristics
- electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
- SVS (supply voltage supervisor/monitor)
- typical characteristics
- main DCO characteristics
- DCO when using ROSC ( see Note 1)
- crystal oscillator, LFXT1 oscillator (see Note 1)
- crystal oscillator, XT2 oscillator (see Note 1)
- USART0, USART1 (see Note 1)
- 12-bit ADC, power supply and input range conditions (see Note 1)
- 12-bit ADC, external reference (see Note 1)
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications (see Figure 19)
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 ( see Figure 23 and Figure 24)
- 12-bit DAC, dynamic specifications continued ( TA = 25
- Flash Memory
- JTAG Interface
- JTAG Fuse (see Note 1)
- APPLICATION INFORMATION
- input/output schematic
- port P1, P1.0 to P1.7, input/output with Schmitt-trigger
- port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
- port P2, P2.3 to P2.4, input/output with Schmitt-trigger
- port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
- port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
- port P3, P3.1, input/output with Schmitt-trigger
- port P3, P3.2, input/output with Schmitt-trigger
- port P3, P3.3, input/output with Schmitt-trigger
- port P4, P4.0 to P4.6, input/output with Schmitt-trigger
- port P4, P4.7, input/output with Schmitt-trigger
- port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
- port P5, P5.1, input/output with Schmitt-trigger
- port P5, P5.2, input/output with Schmitt-trigger
- port P5, P5.3, input/output with Schmitt-trigger
- port P6, P6.0 to P6.5, input/output with Schmitt-trigger
- port P6, P6.6, input/output with Schmitt-trigger
- port P6, P6.7, input/output with Schmitt-trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
- JTAG fuse check mode
- THERMAL PAD MECHANICAL DATA RTD (S-PQFP-N64)
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D
Ultralow-Power Consumption:
- Active Mode: 330
A at 1 MHz, 2.2 V
- Standby Mode: 1.1
A
- Off Mode (RAM Retention): 0.2
A
D
Five Power-Saving Modes
D
Wake-Up From Standby Mode in less
than 6
s
D
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
D
Three-Channel Internal DMA
D
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
D
Dual 12-Bit D/A Converters With
Synchronization
D
16-Bit Timer_A With Three
Capture/Compare Registers
D
16-Bit Timer_B With Three or Seven
Capture/Compare-With-Shadow Registers
D
On-Chip Comparator
D
Serial Communication Interface (USART0),
Functions as Asynchronous UART or
Synchronous SPI or I
2
C
TM
Interface
D
Serial Communication Interface (USART1),
Functions as Asynchronous UART or
Synchronous SPI Interface
D
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D
Brownout Detector
D
Bootstrap Loader
I
2
C is a registered trademark of Philips Incorporated.
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D
Family Members Include:
- MSP430F155:
16KB+256B Flash Memory
512B RAM
- MSP430F156:
24KB+256B Flash Memory
1KB RAM
- MSP430F157:
32KB+256B Flash Memory,
1KB RAM
- MSP430F167:
32KB+256B Flash Memory,
1KB RAM
- MSP430F168:
48KB+256B Flash Memory,
2KB RAM
- MSP430F169:
60KB+256B Flash Memory,
2KB RAM
- MSP430F1610:
32KB+256B Flash Memory
5KB RAM
- MSP430F1611:
48KB+256B Flash Memory
10KB RAM
- MSP430F1612:
55KB+256B Flash Memory
5KB RAM
D
Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN (see Available Options)
D
For Complete Module Descriptions, See the
MSP430x1xx Family User's Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6
s.
The MSP430x15x/16x/161x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit
A/D converter, dual 12-bit D/A converter, one or two universal serial synchronous/asynchronous
communication interfaces (USART), I
2
C, DMA, and 48 I/O pins. In addition, the MSP430x161x series offers
extended RAM addressing for memory-intensive applications and large C-stack requirements.
Typical applications include sensor systems, industrial control applications, hand-held meters, etc.
Copyright
2002 - 2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 64-PIN QFP (PM)
PLASTIC 64-PIN QFN (RTD)
-40
C to 85
C
MSP430F155IPM
MSP430F156IPM
MSP430F157IPM
MSP430F167IPM
MSP430F168IPM
MSP430F169IPM
MSP430F1610IPM
MSP430F1611IPM
MSP430F1612IPM
MSP430F155IRTD
MSP430F156IRTD
MSP430F157IRTD
MSP430F167IRTD
MSP430F168IRTD
MSP430F169IRTD
MSP430F1610IRTD
MSP430F1611IRTD
MSP430F1612IRTD
Product Preview
pin designation, MSP430F155, MSP430F156, and MSP430F157
17 18 19
P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
V
REF+
XIN
XOUT
Ve
REF+
V
REF-
/Ve
REF-
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
63 62 61 60 59
64
58
56 55 54
57
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AV
CC
DV
SS
AV
SS
P6.2/A2
P6.1/A1
P6.0/A0
RST
/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/T
A0
P1.6/T
A1
P1.7/T
A2
P2.0/ACLK
P2.1/T
AINCLK
P2.2/CAOUT/T
A0
P2.3/CA0/T
A1
P2.4/CA1/T
A2
P2.5/R
OSC
P2.6/ADC12CLK/DMAE0
P2.7/T
A0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pin designation, MSP430F167, MSP430F168, MSP430F169
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
V
REF+
XIN
XOUT
Ve
REF+
V
REF-
/Ve
REF-
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
63 62 61 60 59
64
58
56 55 54
57
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AV
CC
DV
SS
AV
SS
P6.2/A2
P6.1/A1
P6.0/A0
RST
/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/T
A0
P1.6/T
A1
P1.7/T
A2
P2.0/ACLK
P2.1/T
AINCLK
P2.2/CAOUT/T
A0
P2.3/CA0/T
A1
P2.4/CA1/T
A2
P2.5/R
OSC
P2.6/ADC12CLK/DMAE0
P2.7/T
A0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pin designation, MSP430F1610, MSP430F1611, MSP430F1612
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6/DAC0
P6.7/A7/DAC1/SVSIN
V
REF+
XIN
XOUT
Ve
REF+
V
REF-
/Ve
REF-
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
63 62 61 60 59
64
58
56 55 54
57
25 26 27 28 29
53 52 51 50 49
30 31 32
PM, RTD PACKAGE
(TOP VIEW)
AV
CC
DV
SS
AV
SS
P6.2/A2
P6.1/A1
P6.0/A0
RST
/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
P1.5/T
A0
P1.6/T
A1
P1.7/T
A2
P2.0/ACLK
P2.1/T
AINCLK
P2.2/CAOUT/T
A0
P2.3/CA0/T
A1
P2.4/CA1/T
A2
P2.5/R
OSC
P2.6/ADC12CLK/DMAE0
P2.7/T
A0
P3.0/STE0
P3.1/SIMO0/SDA
P3.2/SOMI0
P3.3/UCLK0/SCL
P3.4/UTXD0
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagrams
MSP430x15x
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN
XOUT
P3
P4
P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5
P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
32KB Flash
24KB Flash
16KB Flash
1KB RAM
1KB RAM
512B RAM
ADC12
12-Bit
8 Channels
<10
s Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
A
USART0
UART Mode
SPI Mode
I
2
C Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8
8
8
8
8
8
MSP430x16x
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN
XOUT
P3
P4
P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5
P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
60KB Flash
48KB Flash
32KB Flash
2KB RAM
2KB RAM
1KB RAM
ADC12
12-Bit
8 Channels
<10
s Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
A
USART0
UART Mode
SPI Mode
I
2
C Mode
USART1
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8
8
8
8
8
8
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagrams (continued)
MSP430x161x
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN
XOUT
P3
P4
P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5
P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
55KB Flash
48KB Flash
32KB Flash
5KB RAM
10KB RAM
5KB RAM
ADC12
12-Bit
8 Channels
<10
s Conv.
DAC12
12-Bit
2 Channels
Voltage out
DMA
Controller
3 Channels
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
SVS
Brownout
Comparator
A
USART0
UART Mode
SPI Mode
I
2
C Mode
USART1
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8
8
8
8
8
8
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AV
CC
64
Analog supply voltage, positive terminal. Supplies only the analog portion of ADC12 and DAC12.
AV
SS
62
Analog supply voltage, negative terminal. Supplies only the analog portion of ADC12 and DAC12.
DV
CC
1
Digital supply voltage, positive terminal. Supplies all digital parts.
DV
SS
63
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK
20
I/O
General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
P2.3/CA0/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/Rosc
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
P2.6/ADC12CLK/
DMAE0
26
I/O
General-purpose digital I/O pin/conversion clock 12-bit ADC/DMA channel 0 external trigger
P2.7/TA0
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
28
I/O
General-purpose digital I/O pin/slave transmit enable USART0/SPI mode
P3.1/SIMO0/SDA
29
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode, I
2
C data - USART0/I
2
C mode
P3.2/SOMI0
30
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0/SCL
31
I/O
General-purpose digital I/O pin/external clock input - USART0/UART or SPI mode, clock output
USART0/SPI mode, I
2
C clock - USART0/I
2
C mode
P3.4/UTXD0
32
I/O
General-purpose digital I/O pin/transmit data out USART0/UART mode
P3.5/URXD0
33
I/O
General-purpose digital I/O pin/receive data in USART0/UART mode
P3.6/UTXD1
34
I/O
General-purpose digital I/O pin/transmit data out USART1/UART mode
P3.7/URXD1
35
I/O
General-purpose digital I/O pin/receive data in USART1/UART mode
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3/TB3
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare: Out3 output
P4.4/TB4
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare: Out4 output
P4.5/TB5
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare: Out5 output
P4.6/TB6
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare: Out6 output
P4.7/TBCLK
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/STE1
44
I/O
General-purpose digital I/O pin/slave transmit enable USART1/SPI mode
P5.1/SIMO1
45
I/O
General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
P5.2/SOMI1
46
I/O
General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
P5.3/UCLK1
47
I/O
General-purpose digital I/O pin/external clock input USART1/UART or SPI mode, clock output
USART1/SPI mode
16x, 161x devices only
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/
SVSOUT
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance - Timer_B TB0 to
TB6/SVS comparator output
P6.0/A0
59
I/O
General-purpose digital I/O pin/analog input a0 12-bit ADC
P6.1/A1
60
I/O
General-purpose digital I/O pin/analog input a1 12-bit ADC
P6.2/A2
61
I/O
General-purpose digital I/O pin/analog input a2 12-bit ADC
P6.3/A3
2
I/O
General-purpose digital I/O pin/analog input a3 12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O pin/analog input a4 12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O pin/analog input a5 12-bit ADC
P6.6/A6/DAC0
5
I/O
General-purpose digital I/O pin/analog input a6 12-bit ADC/DAC12.0 output
P6.7/A7/DAC1/
SVSIN
6
I/O
General-purpose digital I/O pin/analog input a7 12-bit ADC/DAC12.1 output/SVS input
RST/NMI
58
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK
57
I
Test clock. TCK is the clock input port for device programming test and bootstrap loader start
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
Test data output port. TDO/TDI data output or programming data input terminal
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
Ve
REF+
10
I
Input for an external reference voltage
V
REF+
7
O
Output of positive terminal of the reference voltage in the ADC12
V
REF-
/Ve
REF-
11
I
Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external
applied reference voltage
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
XT2IN
53
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
QFN Pad
NA
NA
QFN package pad connection to DV
SS
recommended (RTD package only)
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 ---> R5
Single operands, destination only
e.g. CALL R8
PC -->(TOS), R8--> PC
Relative jump, un/conditional
e.g. JNE
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
OPERATION
Register
D D
MOV Rs,Rd
MOV R10,R11
R10 --> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)--> M(6+R6)
Symbolic (PC relative)
D D
MOV EDE,TONI
M(EDE) --> M(TONI)
Absolute
D D
MOV &MEM,&TCDAT
M(MEM) --> M(TCDAT)
Indirect
D
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) --> M(Tab+R6)
Indirect
autoincrement
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) --> R11
R10 + 2--> R10
Immediate
D
MOV #X,TONI
MOV #45,TONI
#45 --> M(TONI)
NOTE: S = source D = destination
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
Active mode AM;
-
All clocks are active
D
Low-power mode 0 (LPM0);
-
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
Low-power mode 1 (LPM1);
-
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO's dc-generator is disabled if DCO not used in active mode
D
Low-power mode 2 (LPM2);
-
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator remains enabled
ACLK remains active
D
Low-power mode 3 (LPM3);
-
CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
ACLK remains active
D
Low-power mode 4 (LPM4);
-
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
Crystal oscillator is stopped
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh - 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 & 3)
OFIFG (see Notes 1 & 3)
ACCVIFG (see Notes 1 & 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B7 (see Note 5)
TBCCR0 CCIFG
(see Note 2)
Maskable
0FFFAh
13
Timer_B7 (see Note 5)
TBCCR1 to TBCCR6
CCIFGs, TBIFG
(see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
I
2
C transmit/receive/others
UTXIFG0
I2CIFG (see Note 4)
Maskable
0FFF0h
8
ADC12
ADC12IFG
(see Notes 1 & 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG
(see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
4
USART1 receive
URXIFG1
Maskable
0FFE6h
3
USART1 transmit
UTXIFG1
Maskable
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
0FFE2h
1
DAC12
DMA
DAC12_0IFG,
DAC12_1IFG
DMA0IFG, DMA1IFG,
DMA2IFG (see Notes 1 & 2)
Maskable
0FFE0h
0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. I
2
C interrupt flags located in the module
5. Timer_B7 in MSP430x16x/161x family has 7 CCRs; Timer_B3 in MSP430x15x family has 3 CCRs; in Timer_B3 there are only
interrupt flags TBCCR0, 1 and 2 CCIFGs and the interrupt-enable bits TBCCR0, 1 and 2 CCIEs.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
6
5
4
0
UTXIE0
OFIE
WDTIE
3
2
1
rw-0
rw-0
rw-0
Address
0h
URXIE0
ACCVIE
NMIIE
rw-0
rw-0
rw-0
WDTIE:
Watchdog timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as general-purpose timer.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash memory access violation interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
6
5
4
0
UTXIE1
3
2
1
rw-0
rw-0
Address
01h
URXIE1
URXIE1
:
USART1: UART and SPI receive-interrupt enable
UTXIE1:
USART1: UART and SPI transmit-interrupt enable
URXIE1 and UTXIE1 are not present in MSP430x15x devices.
interrupt flag register 1 and 2
7
6
5
4
0
UTXIFG0
OFIFG
WDTIFG
3
2
1
rw-0
rw-1
rw-(0)
Address
02h
URXIFG0
NMIIFG
rw-1
rw-0
WDTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation
Reset on V
CC
power-on, or a reset condition at the RST/NMI pin in reset mode
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
7
6
5
4
0
UTXIFG1
3
2
1
rw-1
rw-0
Address
03h
URXIFG1
URXIFG1
:
USART1: UART and SPI receive flag
UTXIFG1: USART1: UART and SPI transmit flag
URXIFG1 and UTXIFG1 are not present in MSP430x15x devices.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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module enable registers 1 and 2
7
6
5
4
0
UTXE0
3
2
1
rw-0
rw-0
Address
04h
URXE0
USPIE0
URXE0:
USART0: UART mode receive enable
UTXE0:
USART0: UART mode transmit enable
USPIE0:
USART0: SPI mode transmit and receive enable
7
6
5
4
0
UTXE1
3
2
1
rw-0
rw-0
Address
05h
URXE1
USPIE1
URXE1
:
USART1: UART mode receive enable
UTXE1:
USART1: UART mode transmit enable
USPIE1:
USART1: SPI mode transmit and receive enable
URXE1, UTXE1, and USPIE1 are not present in MSP430x15x devices.
rw-0:
Legend: rw:
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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memory organization (MSP430F15x)
MSP430F155
MSP430F156
MSP430F157
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh - 0FFE0h
0FFFFh - 0C000h
24KB
0FFFFh - 0FFE0h
0FFFFh - 0A000h
32KB
0FFFFh - 0FFE0h
0FFFFh - 08000h
Information memory
Size
Flash
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
Boot memory
Size
ROM
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
RAM
Size
512B
03FFh - 0200h
1KB
05FFh - 0200h
1KB
05FFh - 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
memory organization (MSP430F16x)
MSP430F167
MSP430F168
MSP430F169
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh - 0FFE0h
0FFFFh - 08000h
48KB
0FFFFh - 0FFE0h
0FFFFh - 04000h
60KB
0FFFFh - 0FFE0h
0FFFFh - 01100h
Information memory
Size
Flash
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
Boot memory
Size
ROM
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
RAM
Size
1KB
05FFh - 0200h
2KB
09FFh - 0200h
2KB
09FFh - 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
memory organization (MSP430F161x)
MSP430F1610
MSP430F1611
MSP430F1612
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh - 0FFE0h
0FFFFh - 08000h
48KB
0FFFFh - 0FFE0h
0FFFFh - 04000h
55KB
0FFFFh - 0FFE0h
0FFFFh - 02500h
RAM (Total)
Size
5KB
024FFh - 01100h
10KB
038FFh - 01100h
5KB
024FFh - 01100h
Extended
Size
3KB
024FFh - 01900h
8KB
038FFh - 01900h
3KB
024FFh - 01900h
Mirrored
Size
2KB
018FFh - 01100h
2KB
018FFh - 01100h
2KB
018FFh - 01100h
Information memory
Size
Flash
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
256 Byte
010FFh - 01000h
Boot memory
Size
ROM
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
1KB
0FFFh - 0C00h
RAM
(mirrored at
018FFh - 01100h)
Size
2KB
09FFh - 0200h
2KB
09FFh - 0200h
2KB
09FFh - 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
01FFh - 0100h
0FFh - 010h
0Fh - 00h
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
PM, RTD Package Pins
Data Transmit
13 - P1.1
Data Receive
22 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
D
Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
w/ Interrupt Vectors
Segment 1
Segment 2
Segment n-1
Segment n
Segment A
Segment B
Main
Memory
Info
Memory
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
08400h
083FFh
08200h
081FFh
08000h
024FFh
01100h
010FFh
01080h
0107Fh
01000h
04400h
043FFh
04200h
041FFh
04000h
038FFh
01100h
010FFh
01080h
0107Fh
01000h
RAM
('F161x
only)
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
60KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
04400h
043FFh
04200h
041FFh
04000h
010FFh
01080h
0107Fh
01000h
01400h
013FFh
01200h
011FFh
01100h
010FFh
01080h
0107Fh
01000h
24KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0A400h
0A3FFh
0A200h
0A1FFh
0A000h
010FFh
01080h
0107Fh
01000h
08400h
083FFh
08200h
081FFh
08000h
010FFh
01080h
0107Fh
01000h
16KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
0C000h
010FFh
01080h
0107Fh
01000h
MSP430F161x
MSP430F15x and MSP430F16x
55KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
02800h
027FFh
02600h
025FFh
02500h
024FFh
01100h
010FFh
01080h
0107Fh
01000h
MSP430F169 and MSP430F1612 flash segment n = 256 bytes.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number
SLAU049.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430x15x and MSP430x16x(x) family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator
(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements
of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source
and stabilizes in less than 6
s. The basic clock module provides the following clock signals:
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D
Main clock (MCLK), the system clock used by the CPU.
D
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
CC
may not
have ramped to V
CC(min)
at that time. The user must insure the default DCO settings are not changed until V
CC
reaches V
CC(min)
. If desired, the SVS circuit can be used to determine when V
CC
reaches V
CC(min)
.
digital I/O
There are six 8-bit I/O ports implemented--ports P1 through P6:
D
All individual I/O bits are independently programmable.
D
Any combination of input, output, and interrupt conditions is possible.
D
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D
Read/write access to port-control registers is supported by all instructions.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
hardware multiplier (MSP430x16x/161x Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16
16,
16
8, 8
16, and 8
8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
USART0
The MSP430x15x and the MSP430x16x(x) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered
transmit and receive channels.
The I
2
C support is compliant with the Philips I
2
C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit and 10-bit device addressing modes are supported,
as well as master and slave modes. The USART0 also supports 16-bit-wide I
2
C data transfers and has two
dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I
2
C
mode.
USART1 (MSP430x16x/161x Only)
The MSP430x16x(x) devices have a second hardware universal synchronous/asynchronous receive transmit
(USART1) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels. With the exception of I2C support, operation of USART1 is identical to USART0.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
Module Block
Module Output Signal
Output Pin Number
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
13 - P1.1
22 - P2.2
TA0
CCI0B
17 - P1.5
DV
SS
GND
CCR0
TA0
27 - P2.7
DV
CC
V
CC
14 - P1.2
TA1
CCI1A
14 - P1.2
CAOUT (internal)
CCI1B
18 - P1.6
DV
SS
GND
CCR1
TA1
23 - P2.3
DV
CC
V
CC
ADC12 (internal)
15 - P1.3
TA2
CCI2A
15 - P1.3
ACLK (internal)
CCI2B
19 - P1.7
DV
SS
GND
CCR2
TA2
24 - P2.4
DV
CC
V
CC
timer_B3 (MSP430x15x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timer_B7 (MSP430x16x/161x Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3/B7 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
Module Block
Module Output Signal
Output Pin Number
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
36 - P4.0
TB0
CCI0B
ADC12 (internal)
DV
SS
GND
CCR0
TB0
DV
CC
V
CC
37 - P4.1
TB1
CCI1A
37 - P4.1
37 - P4.1
TB1
CCI1B
ADC12 (internal)
DV
SS
GND
CCR1
TB1
DV
CC
V
CC
38 - P4.2
TB2
CCI2A
38 - P4.2
38 - P4.2
TB2
CCI2B
DV
SS
GND
CCR2
TB2
DV
CC
V
CC
39 - P4.3
TB3
CCI3A
39 - P4.3
39 - P4.3
TB3
CCI3B
DV
SS
GND
CCR3
TB3
DV
CC
V
CC
40 - P4.4
TB4
CCI4A
40 - P4.4
40 - P4.4
TB4
CCI4B
DV
SS
GND
CCR4
TB4
DV
CC
V
CC
41 - P4.5
TB5
CCI5A
41 - P4.5
41 - P4.5
TB5
CCI5B
DV
SS
GND
CCR5
TB5
DV
CC
V
CC
42 - P4.6
TB6
CCI6A
42 - P4.6
ACLK (internal)
CCI6B
DV
SS
GND
CCR6
TB6
DV
CC
V
CC
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripheral file map
PERIPHERAL FILE MAP
DMA
DMA channel 2 transfer size
DMA2SZ
01F6h
DMA channel 2 destination address
DMA2DA
01F4h
DMA channel 2 source address
DMA2SA
01F2h
DMA channel 2 control
DMA2CTL
01F0h
DMA channel 1 transfer size
DMA1SZ
01EEh
DMA channel 1 destination address
DMA1DA
01ECh
DMA channel 1 source address
DMA1SA
01EAh
DMA channel 1 control
DMA1CTL
01E8h
DMA channel 0 transfer size
DMA0SZ
01E6h
DMA channel 0 destination address
DMA0DA
01E4h
DMA channel 0 source address
DMA0SA
01E2h
DMA channel 0 control
DMA0CTL
01E0h
DMA module control 1
DMACTL1
0124h
DMA module control 0
DMACTL0
0122h
DAC12
DAC12_1 data
DAC12_1DAT
01CAh
DAC12_1 control
DAC12_1CTL
01C2h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
ADC12
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
Conversion memory 15
ADC12MEM15
015Eh
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
ADC12
ADC memory-control register15
ADC12MCTL15
08Fh
(continued)
ADC memory-control register14
ADC12MCTL14
08Eh
ADC memory-control register13
ADC12MCTL13
08Dh
ADC memory-control register12
ADC12MCTL12
08Ch
ADC memory-control register11
ADC12MCTL11
08Bh
ADC memory-control register10
ADC12MCTL10
08Ah
ADC memory-control register9
ADC12MCTL9
089h
ADC memory-control register8
ADC12MCTL8
088h
ADC memory-control register7
ADC12MCTL7
087h
ADC memory-control register6
ADC12MCTL6
086h
ADC memory-control register5
ADC12MCTL5
085h
ADC memory-control register4
ADC12MCTL4
084h
ADC memory-control register3
ADC12MCTL3
083h
ADC memory-control register2
ADC12MCTL2
082h
ADC memory-control register1
ADC12MCTL1
081h
ADC memory-control register0
ADC12MCTL0
080h
Timer_B7/
Capture/compare register 6
TBCCR6
019Eh
Timer_B3
Capture/compare register 5
TBCCR5
019Ch
(see Note 1)
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 6
TBCCTL6
018Eh
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Timer_A3
Reserved
017Eh
Reserved
017Ch
Reserved
017Ah
Reserved
0178h
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Reserved
016Eh
Reserved
016Ch
Reserved
016Ah
Reserved
0168h
NOTE 1: Timer_B7 in MSP430x16x/161x family has 7 CCRs, Timer_B3 in MSP430x15x family has 3 CCRs.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Timer_A3
Capture/compare control 2
TACCTL2
0166h
(continued)
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Hardware
Sum extend
SUMEXT
013Eh
Multiplier
Result high word
RESHI
013Ch
(MSP430x16x and
Result low word
RESLO
013Ah
MSP430x161x
only)
Second operand
OP2
0138h
only)
Multiply signed +accumulate/operand1
MACS
0136h
Multiply+accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
Flash
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
Watchdog
Watchdog Timer control
WDTCTL
0120h
USART1
Transmit buffer
U1TXBUF
07Fh
(MSP430x16x and
Receive buffer
U1RXBUF
07Eh
MSP430x161x
Baud rate
U1BR1
07Dh
only)
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
USART0
Transmit buffer
U0TXBUF
077h
(UART or
Receive buffer
U0RXBUF
076h
SPI mode)
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
USART0
I2C interrupt vector
I2CIV
011Ch
(I
2
C mode)
I2C slave address
I2CSA
011Ah
I2C own address
I2COA
0118h
I2C data
I2CDR
076h
I2C SCLL
I2CSCLL
075h
I2C SCLH
I2CSCLH
074h
I2C PSC
I2CPSC
073h
I2C data control
I2CDCTL
072h
I2C transfer control
I2CTCTL
071h
USART control
U0CTL
070h
I2C data count
I2CNDAT
052h
I2C interrupt flag
I2CIFG
051h
I2C interrupt enable
I2CIE
050h
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERAL FILE MAP (CONTINUED)
Comparator_A
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
Basic Clock
Basic clock system control2
BCSCTL2
058h
Basic clock system control1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
BrownOUT, SVS
SVS control register (reset by brownout signal)
SVSCTL
055h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
Special Functions
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at V
CC
to V
SS
-0.3 V to 4.1 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note)
-0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal .
2 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
: (unprogrammed device)
-55
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(programmed device)
-40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
SS
. The JTAG fuse-blow voltage, V
FB
, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
V
CC
(AV
CC
= DV
CC
= V
CC
)
MSP430F15x/16x/
161x
1.8
3.6
V
Supply voltage during flash memory programming, V
CC
(AV
CC
= DV
CC
= V
CC
)
MSP430F15x/16x/
161x
2.7
3.6
V
Supply voltage during program execution, SVS enabled (see
Note 1), V
CC
(AV
CC
= DV
CC
= V
CC
)
MSP430F15x/16x/
161x
2
3.6
V
Supply voltage, V
SS
(AV
SS
= DV
SS
= V
SS
)
0
0
V
Operating free-air temperature range, T
A
MSP430F15x/16x/
161x
-40
85
C
LF selected, XTS=0
Watch crystal
32.768
kHz
LFXT1 crystal frequency, f
(LFXT1)
XT1 selected, XTS=1
Ceramic resonator
450
8000
kHz
(see Notes 2 and 3)
XT1 selected, XTS=1
Crystal
1000
8000
kHz
Ceramic resonator
450
8000
XT2 crystal frequency, f
(XT2)
Crystal
1000
8000
kHz
V
CC
= 1.8 V
DC
4.15
Processor frequency (signal MCLK), f
(System)
V
CC
= 3.6 V
DC
8
MHz
NOTES:
1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the V
CC
is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1M
resistor from XOUT to V
SS
is recommended when V
CC
<
2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at V
CC
2.2 V. In XT1 mode,
the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at V
CC
2.8 V.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
1.8 V
3.6 V
2.7 V 3 V
4.15 MHz
8.0 MHz
Supply Voltage - V
Supply voltage range,
'F15x/16x/161x,
during flash memory programming
Supply voltage range,
'F15x/16x/161x, during
program execution
Figure 1. Frequency vs Supply Voltage, MSP430F15x/16x/161x
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F15x/16x supply current into AV
CC
+ DV
CC
excluding external current (AV
CC
= DV
CC
= V
CC
)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Active mode, (see Note 1)
f
= f
= 1 MHz,
V
CC
= 2.2 V
330
400
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
f
(ACLK)
= 32,768 Hz
XTS=0, SELM=(0,1)
T
A
= -40
C to 85
C
V
CC
= 3 V
500
600
A
I
(AM)
Active mode, (see Note 1)
f
= f
= 4,096 Hz,
V
CC
= 2.2 V
2.5
7
f
(MCLK)
= f
(SMCLK)
= 4,096 Hz,
f
(ACLK)
= 4,096 Hz
XTS=0, SELM=3
T
A
= -40
C to 85
C
V
CC
= 3 V
9
20
A
Low-power mode, (LPM0)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 1 MHz,
V
CC
= 2.2 V
50
60
I
(LPM0)
f
(ACLK)
= 32,768 Hz
XTS=0, SELM=(0,1)
(see Note 1)
T
A
= -40
C to 85
C
V
CC
= 3 V
75
90
A
Low-power mode, (LPM2),
V
CC
= 2.2 V
11
14
I
(LPM2)
f
(MCLK)
= f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 32.768 Hz, SCG0 = 0
T
A
= -40
C to 85
C
V
CC
= 3 V
17
22
A
T
A
= -40
C
1.1
1.6
T
A
= 25
C
V
CC
= 2.2 V
1.1
1.6
Low-power mode, (LPM3)
f
= f
= 0 MHz,
T
A
= 85
C
V
CC
= 2.2 V
2.2
3.0
I
(LPM3)
f
(MCLK)
= f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 32,768 Hz, SCG0 = 1
T
A
= -40
C
2.2
2.8
A
(ACLK)
(see Note 2)
T
A
= 25
C
V
CC
= 3 V
2.0
2.6
T
A
= 85
C
V
CC
= 3 V
3.0
4.3
T
A
= -40
C
0.1
0.5
I
(LPM4)
Low-power mode, (LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz,
T
A
= 25
C
V
CC
=
0.2
0.5
A
I
(LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 0 Hz, SCG0 = 1
T
A
= 85
C
2.2V / 3 V
1.3
2.5
A
NOTES:
1. Timer_B is clocked by f
(DCOCLK)
= 1 MHz. All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current.
2. WDT is clocked by f
(ACLK)
= 32,768 Hz. All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version
I(AM) = I(AM) [1 MHz]
f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version
I
(AM)
= I
(AM) [3 V]
+ 210
A/V
(V
CC
3 V)
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
MSP430F161x supply current into AV
CC
+ DV
CC
excluding external current (AV
CC
= DV
CC
= V
CC
)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Active mode, (see Note 1)
f
= f
= 1 MHz,
V
CC
= 2.2 V
330
400
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
f
(ACLK)
= 32,768 Hz
XTS=0, SELM=(0,1)
T
A
= -40
C to 85
C
V
CC
= 3 V
500
600
A
I
(AM)
Active mode, (see Note 1)
f
= f
= 4,096 Hz,
V
CC
= 2.2 V
2.5
7
f
(MCLK)
= f
(SMCLK)
= 4,096 Hz,
f
(ACLK)
= 4,096 Hz
XTS=0, SELM=3
T
A
= -40
C to 85
C
V
CC
= 3 V
9
20
A
Low-power mode, (LPM0)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 1 MHz,
V
CC
= 2.2 V
50
60
I
(LPM0)
f
(ACLK)
= 32,768 Hz
XTS=0, SELM=(0,1)
(see Note 1)
T
A
= -40
C to 85
C
V
CC
= 3 V
75
95
A
Low-power mode, (LPM2),
V
CC
= 2.2 V
11
14
I
(LPM2)
f
(MCLK)
= f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 32.768 Hz, SCG0 = 0
T
A
= -40
C to 85
C
V
CC
= 3 V
17
22
A
T
A
= -40
C
1.3
1.6
T
A
= 25
C
V
CC
= 2.2 V
1.3
1.6
Low-power mode, (LPM3)
f
= f
= 0 MHz,
T
A
= 85
C
V
CC
= 2.2 V
3.0
6.0
I
(LPM3)
f
(MCLK)
= f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 32,768 Hz, SCG0 = 1
T
A
= -40
C
2.6
3.0
A
(ACLK)
(see Note 2)
T
A
= 25
C
V
CC
= 3 V
2.6
3.0
T
A
= 85
C
V
CC
= 3 V
4.4
8.0
T
A
= -40
C
0.2
0.5
I
(LPM4)
Low-power mode, (LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz,
T
A
= 25
C
V
CC
=
0.2
0.5
A
I
(LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz,
f
(ACLK)
= 0 Hz, SCG0 = 1
T
A
= 85
C
2.2V / 3 V
2.0
5.0
A
NOTES:
1. Timer_B is clocked by f
(DCOCLK)
= 1 MHz. All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current.
2. WDT is clocked by f
(ACLK)
= 32,768 Hz. All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version
I(AM) = I(AM) [1 MHz]
f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version
I
(AM)
= I
(AM) [3 V]
+ 210
A/V
(V
CC
3 V)
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs - Ports P1, P2, P3, P4, P5, P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
= 2.2 V
1.1
1.5
V
IT+
Positive-going input threshold voltage
V
CC
= 3 V
1.5
1.98
V
V
CC
= 2.2 V
0.4
0.9
V
IT-
Negative-going input threshold voltage
V
CC
= 3 V
0.9
1.3
V
V
CC
= 2.2 V
0.3
1.1
V
hys
Input voltage hysteresis (V
IT+
- V
IT-
)
V
CC
= 3 V
0.5
1
V
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Port P1, P2: P1.x to P2.x, external trigger signal
2.2 V
62
t
(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
3 V
50
ns
TA0, TA1, TA2
2.2 V
62
t
(cap)
Timer_A, Timer_B capture
timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2)
3 V
50
ns
f
(TAext)
Timer_A, Timer_B clock
2.2 V
8
f
(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK:
t
(H)
= t
(L)
3 V
10
MHz
f
(TAint)
Timer_A, Timer_B clock
2.2 V
8
f
(TBint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t
(int)
parameters are met. It may be set even with trigger signals
shorter than t
(int)
.
2. Seven capture/compare registers in 'x16x/161x and three capture/compare registers in 'x15x.
leakage current - Ports P1, P2, P3, P4, P5 and P6 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
lkg(Px.y)
Leakage
current
Port Px
V
(Px.y)
(see Note 2)
V
CC
= 2.2 V/3 V
50
nA
NOTES:
1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
OH(max)
= -1.5 mA,
V
CC
= 2.2 V,
See Note 1
V
CC
-0.25
V
CC
I
OH(max)
= -6 mA,
V
CC
= 2.2 V,
See Note 2
V
CC
-0.6
V
CC
V
OH
High-level output voltage
I
OH(max)
= -1.5 mA,
V
CC
= 3 V,
See Note 1
V
CC
-0.25
V
CC
V
I
OH(max)
= -6 mA,
V
CC
= 3 V,
See Note 2
V
CC
-0.6
V
CC
I
OL(max)
= 1.5 mA,
V
CC
= 2.2 V,
See Note 1
V
SS
V
SS
+0.25
I
OL(max)
= 6 mA,
V
CC
= 2.2 V,
See Note 2
V
SS
V
SS
+0.6
V
OL
Low-level output voltage
I
OL(max)
= 1.5 mA,
V
CC
= 3 V,
See Note 1
V
SS
V
SS
+0.25
V
I
OL(max)
= 6 mA,
V
CC
= 3 V,
See Note 2
V
SS
V
SS
+0.6
NOTES:
1. The maximum total current, I
OH(max)
and I
OL(max),
for all outputs combined, should not exceed
12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, I
OH(max)
and I
OL(max),
for all outputs combined, should not exceed
48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
L
= 20 pF,
f
(Px.y)
(1
x
6, 0
y
7)
C
L
= 20 pF,
I
L
=
1.5 mA
V
CC
= 2.2 V / 3 V
DC
f
System
MHz
f
(ACLK)
P2.0/ACLK, P5.6/ACLK
f
System
f
(MCLK)
f
(SMCLK)
P5.4/MCLK,
P1.4/SMCLK, P5.5/SMCLK
C
L
= 20 pF
V
CC
= 2.2 V / 3 V
f
System
MHz
f
(ACLK)
= f
(LFXT1)
= f
(XT1)
40%
60%
P1.0/TACLK
C
L
= 20 pF
f
(ACLK)
= f
(LFXT1)
= f
(LF)
30%
70%
C
L
= 20 pF
V
CC
= 2.2 V / 3 V
f
(ACLK)
= f
(LFXT1)
50%
P1.1/TA0/MCLK,
f
(MCLK)
= f
(XT1)
40%
60%
t
(Xdc)
Duty cycle of output frequency
P1.1/TA0/MCLK,
C
L
= 20 pF,
V
CC
= 2.2 V / 3 V
f
(MCLK)
= f
(DCOCLK)
50%-
15 ns
50%
50%+
15 ns
P1.4/TBCLK/SMCLK,
f
(SMCLK)
= f
(XT2)
40%
60%
P1.4/TBCLK/SMCLK,
C
L
= 20 pF,
V
CC
= 2.2 V / 3 V
f
(SMCLK)
= f
(DCOCLK)
50%-
15 ns
50%
50%+
15 ns
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6 (continued)
Figure 2
V
OL
- Low-Level Output Voltage - V
0
5
10
15
20
25
0.0
0.5
1.0
1.5
2.0
2.5
V
CC
= 2.2 V
P3.5
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
T
A
= 25
C
T
A
= 85
C
OLI
-
Low-Level Output Current
-
mA
Figure 3
V
OL
- Low-Level Output Voltage - V
0
10
20
30
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
CC
= 3 V
P3.5
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
T
A
= 25
C
T
A
= 85
C
OLI
-
Low-Level Output Current
-
mA
Figure 4
V
OH
- High-Level Output Voltage - V
-25
-20
-15
-10
-5
0
0.0
0.5
1.0
1.5
2.0
2.5
V
CC
= 2.2 V
P3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
T
A
= 25
C
T
A
= 85
C
OHI
-
High-Level Output Current
-
mA
Figure 5
V
OH
- High-Level Output Voltage - V
-45
-35
-25
-15
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
CC
= 3 V
P3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
T
A
= 25
C
T
A
= 85
C
OHI
-
High-Level Output Current
-
mA
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
(LPM3)
Delay time
V
CC
= 2.2 V/3 V,
f
DCO
f
DCO43
6
s
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRAMh
CPU HALTED (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
= 2.2 V
25
40
I
(DD)
CAON=1, CARSEL=0, CAREF=0
V
CC
= 3 V
45
60
A
CAON=1, CARSEL=0,
V
CC
= 2.2 V
30
50
I
(Refladder/Refdiode)
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V
CC
= 3 V
45
71
A
V
(IC)
Common-mode input
voltage
CAON =1
V
CC
= 2.2 V/3 V
0
V
CC
-1
V
V
(Ref025)
Voltage @ 0.25 V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
V
CC
= 2.2 V/3 V
0.23
0.24
0.25
V
(Ref050)
Voltage @ 0.5V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
V
CC
= 2.2 V/3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
V
CC
= 2.2 V
390
480
540
V
(RefVT)
(see Figure 6 and Figure 7)
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 T
A
= 85
C
V
CC
= 3 V
400
490
550
mV
V
(offset)
Offset voltage
See Note 2
V
CC
= 2.2 V/3 V
-30
30
mV
V
hys
Input hysteresis
CAON=1
V
CC
= 2.2 V/3 V
0
0.7
1.4
mV
T
A
= 25
C, Overdrive 10 mV,
V
CC
= 2.2 V
130
210
300
T
A
= 25 C, Overdrive 10 mV,
Without filter: CAF=0
V
CC
= 3 V
80
150
240
ns
t
(response LH)
T
A
= 25
C, Overdrive 10 mV,
V
CC
= 2.2 V
1.4
1.9
3.4
T
A
= 25 C, Overdrive 10 mV,
With filter: CAF=1
V
CC
= 3 V
0.9
1.5
2.6
s
T
A
= 25
C, Overdrive 10 mV,
V
CC
= 2.2 V
130
210
300
T
A
= 25 C, Overdrive 10 mV,
Without filter: CAF=0
V
CC
= 3 V
80
150
240
ns
t
(response HL)
T
A
= 25
C, Overdrive 10 mV,
V
CC
= 2.2 V
1.4
1.9
3.4
T
A
= 25 C, Overdrive 10 mV,
With filter: CAF=1
V
CC
= 3 V
0.9
1.5
2.6
s
NOTES:
1. The leakage current for the Comparator_A terminals is identical to I
lkg(Px.x)
specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
T
A
- Free-Air Temperature -
C
400
450
500
550
600
650
-45
-25
-5
15
35
55
75
95
V
CC
= 3 V
Figure 6. V
(RefVT)
vs Temperature, V
CC
= 3 V
V
(REFVT)
-
Reference V
olts
-
mV
Typical
Figure 7. V
(RefVT)
vs Temperature, V
CC
= 2.2 V
T
A
- Free-Air Temperature -
C
400
450
500
550
600
650
-45
-25
-5
15
35
55
75
95
V
CC
= 2.2 V
V
(REFVT)
-
Reference V
olts
-
mV
Typical
_
+
CAON
0
1
V+
0
1
CAF
Low Pass Filter
2.0
s
To Internal
Modules
Set CAIFG
Flag
CAOUT
V-
V
CC
1
0 V
0
Figure 8. Block Diagram of Comparator_A Module
Overdrive
V
CAOUT
t
(response)
V+
V-
400 mV
Figure 9. Overdrive Definition
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
d(BOR)
2000
s
V
CC(Start)
dV
CC
/dt
3 V/s (see Figure 10)
0.7
V
(B_IT-)
V
V
(B_IT-)
dV
CC
/dt
3 V/s (see Figure 10 through Figure 12)
1.71
V
V
hys(B_IT-)
Brownout
dV
CC
/dt
3 V/s (see Figure 10)
70
130
180
mV
t
(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
V
CC
= 2.2 V/3 V
2
s
NOTES:
1. The current consumption of the brownout module is already included in the I
CC
current consumption data. The voltage level V
(B_IT-)
+ V
hys(B_IT-)
is
1.8 V.
2. During power up, the CPU begins code execution following a period of t
BOR(delay)
after
V
CC
= V
(B_IT-)
+ V
hys(B_IT-)
. The
default DCO settings must not be changed until V
CC
V
CC(min)
, where V
CC(min)
is the minimum supply voltage for the desired
operating frequency. See the MSP430x1xx Family User's Guide (SLAU049) for more information on the brownout/SVS circuit.
typical characteristics
0
1
t d(BOR)
VCC
V(B_IT-)
Vhys(B_IT-)
V
CC(Start)
BOR
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical characteristics (continued)
VCC(min)
VCC
3 V
t pw
0
0.5
1
1.5
2
0.001
1
1000
Vcc = 3 V
typical conditions
1 ns
1 ns
t
pw
- Pulse Width -
s
V
CC(min)
-
V
t
pw
- Pulse Width -
s
Figure 11. V
CC(min)
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
0
0.5
1
1.5
2
Vcc = 3 V
typical conditions
VCC(min)
t pw
t
pw
- Pulse Width -
s
V
CC(min)
-
V
3 V
0.001
1
1000
t
f
t
r
t
pw
- Pulse Width -
s
t
f
= t
r
Figure 12. V
CC(min)
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
dV
CC
/dt > 30 V/ms (see Figure 13)
5
150
s
t
(SVSR)
dV
CC
/dt
30 V/ms
2000
s
t
d(SVSon)
SVSON, switch from VLD = 0 to VLD
0, V
CC
= 3 V
20
150
s
t
settle
VLD
0
12
s
V
(SVSstart)
VLD
0, V
CC
/dt
3 V/s (see Figure 13)
1.55
1.7
V
VLD = 1
70
120
155
mV
V
hys(SVS_IT-)
V
CC
/dt
3 V/s (see Figure 13)
VLD = 2 .. 14
V
(SVS_IT-)
x 0.004
V
(SVS_IT-)
x 0.008
V
hys(SVS_IT-)
V
CC
/dt
3 V/s (see Figure 13), External voltage applied
on A7
VLD = 15
4.4
10.4
mV
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
V
CC
/dt
3 V/s (see Figure 13 and Figure 14)
VLD = 8
2.58
2.8
3
V
(SVS_IT-)
VLD = 9
2.69
2.9
3.13
V
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61
VLD = 13
3.24
3.5
3.76
VLD = 14
3.43
3.7
3.99
V
CC
/dt
3 V/s (see Figure 13 and Figure 14), External
voltage applied on A7
VLD = 15
1.1
1.2
1.3
I
CC(SVS)
(see Note 1)
VLD
0, V
CC
= 2.2 V/3 V
10
15
A
The recommended operating voltage range is limited to 3.6 V.
t
settle
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD
0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the I
CC
current consumption data.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical characteristics
VCC(start)
AVCC
V(B_IT-)
Brownout
Region
V(SVSstart)
V(SVS_IT-)
Software sets VLD >0:
SVS is active
td(SVSR)
undefined
Vhys(SVS_IT-)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
out
Region
SVS Circuit is Active From VLD > to V
CC
< V(
B_IT-)
SVS out
V
hys(B_IT-)
Figure 13. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns
1 ns
VCC(min)
t pw
t
pw
- Pulse Width -
s
V
CC(min)
-
V
3 V
1
10
1000
t
f
t
r
t - Pulse Width -
s
100
t pw
3 V
t
f
= t
r
Rectangular Drop
Triangular Drop
VCC(min)
Figure 14. V
CC(min)
: Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V
CC
= 2.2 V
0.08
0.12
0.15
f
(DCO03)
R
sel
= 0, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
0.08
0.13
0.16
MHz
V
CC
= 2.2 V
0.14
0.19
0.23
f
(DCO13)
R
sel
= 1, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
0.14
0.18
0.22
MHz
V
CC
= 2.2 V
0.22
0.30
0.36
f
(DCO23)
R
sel
= 2, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
0.22
0.28
0.34
MHz
V
CC
= 2.2 V
0.37
0.49
0.59
f
(DCO33)
R
sel
= 3, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
0.37
0.47
0.56
MHz
V
CC
= 2.2 V
0.61
0.77
0.93
f
(DCO43)
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
0.61
0.75
0.90
MHz
V
CC
= 2.2 V
1
1.2
1.5
f
(DCO53)
R
sel
= 5, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
1
1.3
1.5
MHz
V
CC
= 2.2 V
1.6
1.9
2.2
f
(DCO63)
R
sel
= 6, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
1.69
2.0
2.29
MHz
V
CC
= 2.2 V
2.4
2.9
3.4
f
(DCO73)
R
sel
= 7, DCO = 3, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
2.7
3.2
3.65
MHz
f
(DCO47)
R
sel
= 4, DCO = 7, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 2.2 V/3 V
f
DCO40
1.7
f
DCO40
2.1
f
DCO40
2.5
MHz
V
CC
= 2.2 V
4
4.5
4.9
f
(DCO77)
R
sel
= 7, DCO = 7, MOD = 0, DCOR = 0, T
A
= 25
C
V
CC
= 3 V
4.4
4.9
5.4
MHz
S
Rsel
S
R
= f
Rsel+1
/ f
Rsel
V
CC
= 2.2 V/3 V
1.35
1.65
2
S
DCO
S
DCO
= f
(DCO+1)
/ f
(DCO)
V
CC
= 2.2 V/3 V
1.07
1.12
1.16
Temperature drift, R
sel
= 4, DCO = 3, MOD = 0
V
CC
= 2.2 V
-0.31
-0.36
-0.40
D
t
Temperature drift, R
sel
= 4, DCO = 3, MOD = 0
(see Note 2)
V
CC
= 3 V
-0.33
-0.38
-0.43
%/
C
D
V
Drift with V
CC
variation, R
sel
= 4, DCO = 3, MOD = 0
(see Note 2)
V
CC
= 2.2 V/3 V
0
5
10
%/V
NOTES:
1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f
(System)
.
2. This parameter is not production tested.
2.2
3
f DCO_0
Max
Min
Max
Min
f DCO_7
DCO
0
1
2
3
4
5
6
7
f DCOCLK
1
V
CC
- V
Frequency V
ariance
Figure 15. DCO Characteristics
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
main DCO characteristics
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
f
(
DCOx0)
to f
(
DCOx7)
are valid for all devices.
D
All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D
DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S
DCO
.
D
Modulation control bits MOD0 to MOD4 select how often f
(
DCO+1)
is used within the period of 32 DCOCLK
cycles. The frequency f
(DCO)
is used for the remaining cycles. The frequency is an average equal to:
f
average
+
32 f
(DCO)
f
(DCO)1)
MOD f
(DCO)
)(32*MOD) f
(DCO)1)
DCO when using R
OSC
(see Note 1)
PARAMETER
TEST CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1,
2.2 V
1.8
15%
MHz
f
DCO
, DCO output frequency
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1,
T
A
= 25
C
3 V
1.95
15%
MHz
D
t
, Temperature drift
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
0.1
%/
C
D
v
, Drift with V
CC
variation
R
sel
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
10
%/V
NOTES:
1. R
OSC
= 100k
. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T
K
=
50ppm/
C.
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
XTS=0; LF oscillator selected, V
CC
= 2.2 V/3 V
12
C
XIN
Integrated input capacitance
XTS=1; XT1 oscillator selected, V
CC
= 2.2 V/3 V
2
pF
XTS=0; LF oscillator selected, V
CC
= 2.2 V/3 V
12
C
XOUT
Integrated output capacitance
XTS=1; XT1 oscillator selected, V
CC
= 2.2 V/3 V
2
pF
V
IL
V
CC
= 2.2 V/3 V
XTS = 0 or 1
XT1 or LF modes
V
SS
0.2
V
CC
Input levels at XIN
CC
(see Note 2)
XTS = 0, LF mode
0.9
V
CC
V
CC
V
V
IH
XTS = 1, XT1 mode
0.8
V
CC
V
CC
NOTES:
1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
C
XIN
Integrated input capacitance
V
CC
= 2.2 V/3 V
2
pF
C
XOUT
Integrated output capacitance
V
CC
= 2.2 V/3 V
2
pF
V
IL
V
SS
0.2
V
CC
V
V
IH
Input levels at XIN
V
CC
= 2.2 V/3 V (see Note 2)
0.8
V
CC
V
CC
V
NOTES:
1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V
CC
= 2.2 V
200
430
800
t
(
)
USART0/USART1: deglitch time
V
CC
= 3 V
150
280
500
ns
NOTE 1: The signal applied to the USART0/USART1 receive signal/terminal (URXD0/1) should meet the timing requirements of t
(
)
to ensure
that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t
(
)
. The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
AV
CC
Analog supply voltage
AV
CC
and DV
CC
are connected together
AV
SS
and DV
SS
are connected together
V
(AVSS)
= V
(DVSS)
= 0 V
2.2
3.6
V
V
(P6.x/Ax)
Analog input voltage
range (see Note 2)
All P6.0/A0 to P6.7/A7 terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
0
x
7; V
(AVSS)
V
P6.x/Ax
V
(AVCC)
0
V
AVCC
V
Operating supply current
f
ADC12CLK
= 5.0 MHz
2.2 V
0.65
1.3
I
ADC12
into AV
CC
terminal
(see Note 3)
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
3 V
0.8
1.6
mA
Operating supply current
f
ADC12CLK
= 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3 V
0.5
0.8
mA
I
REF+
into AV
CC
terminal
(see Note 4)
f
ADC12CLK
= 5.0 MHz
2.2 V
0.5
0.8
(see Note 4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0
3 V
0.5
0.8
mA
C
I
Input capacitance
Only one terminal can be selected
at one time, P6.x/Ax
2.2 V
40
pF
R
I
Input MUX ON resistance
0V
V
Ax
V
AVCC
3 V
2000
Not production tested, limits verified by design
NOTES:
1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V
R+
to V
R-
for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter I
ADC12
.
4. The internal reference current is supplied via terminal AV
CC
. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V
eREF+
Positive external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 2)
1.4
V
AVCC
V
V
REF- /
V
eREF-
Negative external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 3)
0
1.2
V
(V
eREF+
-
V
REF-/
V
eREF-
)
Differential external
reference voltage input
V
eREF+
> V
REF-
/V
eREF-
(see Note 4)
1.4
V
AVCC
V
I
VeREF+
Static input current
0V
V
eREF+
V
AVCC
2.2 V/3 V
1
A
I
VREF-/VeREF-
Static input current
0V
V
eREF-
V
AVCC
2.2 V/3 V
1
A
NOTES:
1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C
i
, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Positive built-in reference
REF2_5V = 1 for 2.5 V
I
VREF+
max
I
VREF+
I
VREF+
min
3 V
2.4
2.5
2.6
V
REF+
Positive built-in reference
voltage output
REF2_5V = 0 for 1.5 V
I
VREF+
max
I
VREF+
I
VREF+
min
2.2 V/3 V
1.44
1.5
1.56
V
REF2_5V = 0, I
VREF+
max
I
VREF+
I
VREF+
min
2.2
AV
CC(min)
AV
CC
minimum voltage,
Positive built-in reference
REF2_5V = 1, -0.5mA
I
VREF+
I
VREF+
min
2.8
V
AV
CC(min)
Positive built-in reference
active
REF2_5V = 1, -1mA
I
VREF+
I
VREF+
min
2.9
V
Load current out of V
REF+
2.2 V
0.01
-0.5
I
VREF+
Load current out of V
REF+
terminal
3 V
0.01
-1
mA
I
VREF+
= 500
A +/- 100
A
2.2 V
2
Load-current regulation
Analog input voltage ~0.75 V;
REF2_5V = 0
3 V
2
LSB
I
L(VREF)+
Load-current regulation
V
REF+
terminal
I
VREF+
= 500
A
100
A
Analog input voltage ~1.25 V;
REF2_5V = 1
3 V
2
LSB
Load current regulation
I
VREF+
=100
A
900
A,
I
DL(VREF) +
Load current regulation
V
REF+
terminal
C
VREF+
=5
F, ax ~0.5 x V
REF+
Error of conversion result
1 LSB
3 V
20
ns
C
VREF+
Capacitance at pin V
REF+
(see Note 1)
REFON =1,
0 mA
I
VREF+
I
VREF+
max
2.2 V/3 V
5
10
F
T
REF+
Temperature coefficient of
built-in reference
I
VREF+
is a constant in the range of
0 mA
I
VREF+
1 mA
2.2 V/3 V
100
ppm/
C
t
REFON
Settle time of internal
reference voltage (see
Figure 16 and Note 2)
I
VREF+
= 0.5 mA, C
VREF+
= 10
F,
V
REF+
= 1.5 V, V
AVCC
= 2.2 V
17
ms
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins V
REF+
and AV
SS
and V
REF-
/V
eREF-
and AV
SS
: 10
F tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after t
REFON
is less than
0.5 LSB. The settling time depends on the external
capacitive load.
C
VREF+
1
F
0
1 ms
10 ms
100 ms
t
REFON
t
REFON
.66 x C
VREF+
[ms] with C
VREF+
in
F
100
F
10
F
Figure 16. Typical Settling Time of Internal Reference t
REFON
vs External Capacitor on V
REF
+
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
+
-
10
F
100 nF
AVSS
MSP430F15x
MSP430F16x
+
-
+
-
10
F
100 nF
10
F
100 nF
AVCC
10
F
100 nF
DVSS
DVCC
From
Power
Supply
Apply
External
Reference
+
-
Apply External Reference [V
eREF+
]
or Use Internal Reference [V
REF+
]
V
REF+
or V
eREF+
V
REF
-/V
eREF-
MSP430F161x
Figure 17. Supply Voltage and Reference Voltage Design V
REF-/
V
eREF-
External Supply
+
-
10
F
100 nF
AVSS
MSP430F15x
MSP430F16x
+
-
10
F
100 nF
AVCC
10
F
100 nF
DVSS
DVCC
From
Power
Supply
+
-
Apply External Reference [V
eREF+
]
or Use Internal Reference [V
REF+
]
V
REF+
or V
eREF+
V
REF-
/V
eREF-
Reference Is Internally
Switched to AV
SS
MSP430F161x
Figure 18. Supply Voltage and Reference Voltage Design V
REF-/
V
eREF-
= AV
SS
, Internally Connected
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
f
ADC12CLK
For specified performance of ADC12
linearity parameters
2.2V/
3 V
0.45
5
6.3
MHz
f
ADC12OSC
Internal ADC12
oscillator
ADC12DIV=0,
f
ADC12CLK
=f
ADC12OSC
2.2 V/
3 V
3.7
5
6.3
MHz
C
VREF+
5
F, Internal oscillator,
f
ADC12OSC
= 3.7 MHz to 6.3 MHz
2.2 V/
3 V
2.06
3.51
s
t
CONVERT
Conversion time
External f
ADC12CLK
from ACLK, MCLK or SMCLK:
ADC12SSEL
0
13
ADC12DIV
1/f
ADC12CLK
s
t
ADC12ON
Turn on settling time of
the ADC
(see Note 1)
100
ns
R
S
= 400
, R
I
= 1000
,
3 V
1220
t
Sample
Sampling time
C
I
= 30 pF
= [R
S
+ R
I
] x C
I;
(see Note 2)
2.2 V
1400
ns
Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:
1. The condition is that the error in a conversion started after t
ADC12ON
is less than
0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (
) are needed to get an error of less than
0.5 LSB:
t
Sample
= ln(2
n+1
) x (R
S
+ R
I
) x C
I
+ 800 ns where n = ADC resolution = 12, R
S
= external source resistance.
12-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
1.4 V
(V
eREF+
- V
REF-
/V
eREF-
) min
1.6 V
2
E
I
Integral linearity error
1.6 V < (V
eREF+
- V
REF-
/V
eREF-
) min
[V
AVCC
]
2.2 V/3 V
1.7
LSB
E
D
Differential linearity
error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
C
VREF+
= 10
F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
1
LSB
E
O
Offset error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
Internal impedance of source R
S
< 100
,
C
VREF+
= 10
F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
2
4
LSB
E
G
Gain error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
C
VREF+
= 10
F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
1.1
2
LSB
E
T
Total unadjusted
error
(V
eREF+
- V
REF-
/V
eREF-
)
min
(V
eREF+
- V
REF-
/V
eREF-
),
C
VREF+
= 10
F (tantalum) and 100 nF (ceramic)
2.2 V/3 V
2
5
LSB
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Operating supply current into
REFON = 0, INCH = 0Ah,
2.2 V
40
120
I
SENSOR
Operating supply current into
AV
CC
terminal (see Note 1)
REFON = 0, INCH = 0Ah,
ADC12ON=NA, T
A
= 25
_
C
3 V
60
160
A
ADC12ON = 1, INCH = 0Ah,
2.2 V
986
V
SENSOR
(see Note 2)
ADC12ON = 1, INCH = 0Ah,
T
A
= 0
C
3 V
986
mV
2.2 V
3.55
3.55
3%
TC
SENSOR
ADC12ON = 1, INCH = 0Ah
3 V
3.55
3.55
3%
mV/
C
Sample time required if channel
ADC12ON = 1, INCH = 0Ah,
2.2 V
30
t
SENSOR(sample)
Sample time required if channel
10 is selected (see Note 3)
Error of conversion result
1
LSB
3 V
30
s
Current into divider at channel 11
2.2 V
NA
I
VMID
Current into divider at channel 11
(see Note 4)
ADC12ON = 1, INCH = 0Bh,
3 V
NA
A
ADC12ON = 1, INCH = 0Bh,
2.2 V
1.1
1.1
0.04
V
MID
AV
CC
divider at channel 11
ADC12ON = 1, INCH = 0Bh,
V
MID
is ~0.5 x V
AVCC
3 V
1.5
1.50
0.04
V
Sample time required if channel
ADC12ON = 1, INCH = 0Bh,
2.2 V
1400
t
VMID(sample)
Sample time required if channel
11 is selected (see Note 5)
Error of conversion result
1
LSB
3 V
1220
ns
Not production tested, limits characterized
NOTES:
1. The sensor current I
SENSOR
is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, I
SENSOR
is already included in I
REF+
.
2. The temperature sensor offset can be as much as
20
_
C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 k
. The sample time required includes the sensor-on time t
SENSOR(on)
4. No additional current is needed. The V
MID
is used during sampling.
5. The on-time t
VMID(on)
is included in the sampling time t
VMID(sample)
; no additional on time is needed.
12-bit DAC, supply specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
AV
CC
Analog supply voltage
AV
CC =
DV
CC
,
AV
SS
= DV
SS
=0 V
2.20
3.60
V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
50
110
Supply Current:
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h
,
V
eREF+
=V
REF+
= AV
CC
2.2V/3V
50
110
I
DD
Single DAC Channel
(see Notes 1 and 2)
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, V
eREF+
=V
REF+
= AV
CC
2.2V/3V
200
440
A
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, V
eREF+
=V
REF+
= AV
CC
2.2V/3V
700
1500
Power supply
DAC12_xDAT = 800h, V
REF
= 1.5 V
AV
CC
= 100mV
2.2V
PSRR
rejection ratio
(see Notes 3 and 4)
DAC12_xDAT = 800h, V
REF
= 1.5 V or 2.5 V
AV
CC
= 100mV
3V
70
dB
NOTES:
1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log
{
AV
CC
/
V
DAC12_xOUT
}.
4. V
REF
is applied externally. The internal reference is not used.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
43
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 19)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Resolution
(12-bit Monotonic)
12
bits
Integral nonlinearity
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
INL
Integral nonlinearity
(see Note 1)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
2.0
8.0
LSB
Differential nonlinearity
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
DNL
Differential nonlinearity
(see Note 1)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
0.4
1.0
LSB
Offset voltage w/o
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
E
O
calibration
(see Notes 1, 2)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
21
Offset voltage with
V
ref
= 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
mV
calibration
(see Notes 1, 2)
V
ref
= 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
2.5
d
E(O)
/d
T
Offset error
temperature coefficient
(see Note 1)
2.2V/3V
30
uV/C
V
REF
= 1.5 V
2.2V
E
G
Gain error (see Note 1)
V
REF
= 2.5 V
3V
3.50
% FSR
d
E(G)
/d
T
Gain temperature
coefficient (see Note 1)
2.2V/3V
10
ppm of
FSR/
C
DAC12AMPx=2
2.2V/3V
100
t
Offset_Cal
Time for offset calibration
DAC12AMPx=3,5
2.2V/3V
32
ms
t
Offset_Cal
(see Note 3)
DAC12AMPx=4,6,7
2.2V/3V
6
ms
NOTES:
1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and
"b" of the first order equation: y = a + b*x. V
DAC12_xOUT
= E
O
+ (1 + E
G
) * (V
eREF+
/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
Figure 19. Linearity Test Load Conditions and Gain/Offset Definition
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
DAC12_xDAT - Digital Code
-4
-3
-2
-1
0
1
2
3
4
0
512
1024
1536
2048
2560
3072
3584
V
CC
= 2.2 V, V
REF
= 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4095
INL
-
Integral Nonlinearity Error
-
LSB
DAC12_xDAT - Digital Code
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
512
1024
1536
2048
2560
3072
3584
V
CC
= 2.2 V, V
REF
= 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
4095
DNL
-
Differential Nonlinearity Error
-
LSB
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
No Load, Ve
REF+
= AV
CC
,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.005
Output voltage
range
No Load, Ve
REF+
= AV
CC
,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AV
CC
-0.05
AV
CC
V
V
O
range
(see Note 1,
Figure 22)
R
Load
= 3 k
, Ve
REF+
= AV
CC
,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.1
V
R
Load
= 3 k
, Ve
REF+
= AV
CC
,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AV
CC
-0.13
AV
CC
V
C
L(DAC12)
Max DAC12
load capacitance
2.2V/3V
100
pF
Max DAC12
2.2V
-0.5
+0.5
mA
I
L(DAC12)
Max DAC12
load current
3V
-1.0
+1.0
mA
R
Load
= 3 k
V
O/P(DAC12)
= 0 V
DAC12AMPx = 7
DAC12_xDAT = 0h
2.2V/3V
150
250
R
O/P(DAC12)
Output
Resistance
(see Figure 22)
R
Load
= 3 k
V
O/P(DAC12)
= AV
CC
DAC12AMPx = 7
DAC12_xDAT = 0FFFh
2.2V/3V
150
250
R
Load
= 3 k
0.3 V < V
O/P(DAC12)
< AV
CC
- 0.3 V
DAC12AMPx = 7
2.2V/3V
1
4
NOTES:
1. Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
0.3
AVCC
AVCC -0.3V
VOUT
Min
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12
O/P(DAC12_x)
Figure 22. DAC12_x Output Resistance Tests
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
Reference input
DAC12IR=0, (see Notes 1 and 2)
2.2V/3V
AV
CC
/3
AV
CC
+0.2
Ve
REF+
Reference input
voltage range
DAC12IR=1, (see Notes 3 and 4)
2.2V/3V
AVcc
AVcc+0.2
V
DAC12_0 IR=DAC12_1 IR =0
2.2V/3V
20
M
DAC12_0 IR=1, DAC12_1 IR = 0
2.2V/3V
Ri
(VREF+)
,
Reference input
DAC12_0 IR=0, DAC12_1 IR = 1
2.2V/3V
40
48
56
k
(VREF+)
Ri
(VeREF+)
resistance
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2.2V/3V
20
24
28
k
NOTES:
1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV
CC
).
2. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
- V
E(O)
] / [3*(1 + E
G
)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV
CC
).
4. The maximum voltage applied at reference input voltage terminal Ve
REF+
= [AV
CC
- V
E(O)
] / (1 + E
G
).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; V
ref
= V
CC
, DAC12IR = 1 (see Figure 23 and Figure 24)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
DAC12_xDAT = 800h,
DAC12AMPx=0
{2, 3, 4}
2.2V/3V
60
120
t
ON
DAC12 on-
DAC12_xDAT = 800h,
Error
V(O)
<
0.5 LSB
DAC12AMPx=0
{5, 6}
2.2V/3V
15
30
s
t
ON
time
Error
V(O)
<
0.5 LSB
(see Note 1,Figure 23)
DAC12AMPx=0
7
2.2V/3V
6
12
s
DAC12AMPx=2
2.2V/3V
100
200
t
S(FS)
Settling
DAC12_xDAT =
DAC12AMPx=3,5
2.2V/3V
40
80
s
t
S(FS)
time,full-scale
80h
F7Fh
80h
DAC12AMPx=4,6,7
2.2V/3V
15
30
s
DAC12_xDAT =
DAC12AMPx=2
2.2V/3V
5
t
S(C-C)
Settling time,
DAC12_xDAT =
3F8h
408h
3F8h
DAC12AMPx=3,5
2.2V/3V
2
s
t
S(C-C)
code to code
3F8h
408h
3F8h
BF8h
C08h
BF8h
DAC12AMPx=4,6,7
2.2V/3V
1
s
DAC12AMPx=2
2.2V/3V
0.05
0.12
SR
Slew Rate
DAC12_xDAT =
DAC12AMPx=3,5
2.2V/3V
0.35
0.7
V/
s
SR
Slew Rate
80h
F7Fh
80h
DAC12AMPx=4,6,7
2.2V/3V
1.5
2.7
V/
s
DAC12AMPx=2
2.2V/3V
10
Glitch energy: full-scale
DAC12_xDAT =
DAC12AMPx=3,5
2.2V/3V
10
nV-s
Glitch energy: full-scale
80h
F7Fh
80h
DAC12AMPx=4,6,7
2.2V/3V
10
nV-s
NOTES:
1. R
Load
and C
Load
connected to AV
SS
(not AV
CC
/2) in Figure 23.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AVCC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1
Conversion 2
VOUT
Conversion 3
Glitch
Energy
+/- 1/2 LSB
+/- 1/2 LSB
tsettleLH
tsettleHL
= 3 k
Figure 23. Settling Time and Glitch Energy Testing
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
47
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
VOUT
Conversion 3
10%
tSRLH
tSRHL
90%
10%
90%
Figure 24. Slew Rate Testing
12-bit DAC, dynamic specifications continued (T
A
= 25
C unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
40
BW
-3dB
3-dB bandwidth,
V
DC
=1.5V, V
AC
=0.1V
PP
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
180
kHz
(see Figure 25)
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<->F7Fh, R
Load
= 3k
f
DAC12_1OUT
= 10kHz @ 50/50 duty cycle
2.2V/3V
-80
Channel to channel crosstalk
(see Note 1 and Figure 26)
DAC12_0DAT = 80h<->F7Fh, R
Load
= 3k
,
DAC12_1DAT = 800h, No Load
f
DAC12_0OUT
= 10kHz @ 50/50 duty cycle
2.2V/3V
-80
dB
NOTES:
1. R
LOAD
= 3 k
, C
LOAD
= 100 pF
VeREF+
AC
DC
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12_x
DACx
= 3 k
Figure 25. Test Conditions for 3-dB Bandwidth Specification
DAC12_xDAT 080h
V OUT
fToggle
7F7h
V DAC12_yOUT
080h
7F7h
080h
V DAC12_xOUT
REF+
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12_1
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12_0
DAC0
DAC1
V
Figure 26. Crosstalk Test Conditions
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
48
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
2.7
3.6
V
f
FTG
Flash Timing Generator frequency
257
476
kHz
I
PGM
Supply current from DV
CC
during program
2.7 V/ 3.6 V
3
5
mA
I
ERASE
Supply current from DV
CC
during erase
2.7 V/ 3.6 V
3
7
mA
t
CPT
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
t
CMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
200
ms
Program/Erase endurance
10
4
10
5
cycles
t
Retention
Data retention duration
T
J
= 25
C
100
years
t
Word
Word or byte program time
35
t
Block, 0
Block program time for 1
st
byte or word
30
t
Block, 1-63
Block program time for each additional byte or word
21
t
Block, End
Block program end-sequence wait time
see Note 3
6
t
FTG
t
Mass Erase
Mass erase time
5297
t
Seg Erase
Segment erase time
4819
NOTES:
1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
FTG
,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller's state machine (t
FTG
= 1/f
FTG
).
JTAG Interface
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
2.2 V
0
5
MHz
f
TCK
TCK input frequency
see Note 1
3 V
0
10
MHz
R
Internal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
2.2 V/ 3 V
25
60
90
k
NOTES:
1. f
TCK
may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
PARAMETER
TEST
CONDITIONS
V
CC
MIN
NOM
MAX
UNIT
V
CC(FB)
Supply voltage during fuse-blow condition
T
A
= 25
C
2.5
V
V
FB
Voltage level on TDI/TCLK for fuse-blow: F versions
6
7
V
I
FB
Supply current into TDI/TCLK during fuse blow
100
mA
t
FB
Time to blow fuse
1
ms
NOTES:
1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1.0/TACLK ...
P1IN.x
Module X IN
Pad Logic
Interrupt
Flag
Edge
Select
Interrupt
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1IRQ.x
EN
D
Set
EN
Q
P1OUT.x
P1DIR.x
P1SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
P1.7/TA2
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
DV
SS
P1IN.0
TACLK
P1IE.0
P1IFG.0
P1IES.0
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
Out0 signal
P1IN.1
CCI0A
P1IE.1
P1IFG.1
P1IES.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 signal
P1IN.2
CCI1A
P1IE.2
P1IFG.2
P1IES.2
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal
P1IN.3
CCI2A
P1IE.3
P1IFG.3
P1IES.3
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
Out0 signal
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out1 signal
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
Signal from or to Timer_A
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
50
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2IN.x
P2OUT.x
Pad Logic
P2DIR.x
P2SEL.x
Module X OUT
Edge
Select
Interrupt
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2IRQ.x
Direction Control
P2.0/ACLK
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
Bus Keeper
CAPD.X
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.6/ADC12CLK/DMAE0
P2.7/TA0
0: Input
1: Output
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
From Module
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
unused
P2IE.0
P2IFG.0
P2IES.0
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
DV
SS
P2IN.1
INCLK
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
CAOUT
P2IN.2
CCI0B
P2IE.2
P2IFG.2
P2IES.2
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
ADC12CLK
P2IN.6
DMAE0
#
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
Out0 signal
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
Signal from Comparator_A
Signal to Timer_A
Signal from Timer_A
ADC12CLK signal is output of the 12-bit ADC module
#
Signal to DMA, channel 0, 1 and 2
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
51
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
Bus Keeper
P2IN.3
P2OUT.3
Pad Logic
P2DIR.3
P2SEL.3
Module X OUT
Edge
Select
Interrupt
P2SEL.3
P2IES.3
P2IFG.3
P2IE.3
P2IRQ.3
Direction Control
From Module
P2.3/CA0/TA1
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
P2IN.4
P2OUT.4
Pad Logic
P2DIR.4
P2SEL.4
Module X OUT
Edge
Select
Interrupt
P2SEL.4
P2IES.4
P2IFG.4
P2IE.4
P2IRQ.4
Direction Control
From Module
P2.4/CA1/TA2
0
1
0
1
Interrupt
Flag
Set
EN
Q
Module X IN
EN
D
Comparator_A
-
+
Reference Block
CCI1B
CAF
CAREF
P2CA
CAEX
CAREF
Bus Keeper
CAPD.3
CAPD.4
To Timer_A3
0: Input
1: Output
0: Input
1: Output
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out1 signal
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
P2Sel.4
P2DIR.4
P2DIR.4
P2OUT.4
Out2 signal
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
Signal from Timer_A
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
52
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and R
osc
function for the basic clock module
P2IN.5
P2OUT.5
Pad Logic
P2DIR.5
P2SEL.5
Module X OUT
Edge
Select
Interrupt
P2SEL.5
P2IES.5
P2IFG.5
P2IE.5
P2IRQ.5
Direction Control
P2.5/Rosc
0
1
0
1
Interrupt
Flag
Set
EN
Q
DCOR
Module X IN
EN
D
to
0
1
DC Generator
Bus Keeper
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
Internal to
Basic Clock
Module
V
CC
0: Input
1: Output
From Module
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
DV
SS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
53
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3.0/STE0
P3IN.x
Module X IN
Pad Logic
EN
D
P3OUT.x
P3DIR.x
P3SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
P3.4/UTXD0
P3.5/URXD0
0: Input
1: Output
x: Bit Identifier, 0 and 4 to 7 for Port P3
P3.6/UTXD1
P3.7/URXD1
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P3Sel.0
P3DIR.0
DV
SS
P3OUT.0
DV
SS
P3IN.0
STE0
P3Sel.4
P3DIR.4
DV
CC
P3OUT.4
UTXD0
P3IN.4
Unused
P3Sel.5
P3DIR.5
DV
SS
P3OUT.5
DV
SS
P3IN.5
URXD0
P3Sel.6
P3DIR.6
DV
CC
P3OUT.6
UTXD1
P3IN.6
Unused
P3Sel.7
P3DIR.7
DV
SS
P3OUT.7
DV
SS
P3IN.7
URXD1
Output from USART0 module
Output from USART1 module
Input to USART0 module
Input to USART1 module
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
54
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.1, input/output with Schmitt-trigger
P3.1/SIMO0/SDA
P3IN.1
Pad Logic
EN
D
P3OUT1
P3DIR.1
P3SEL.1
(SI)MO0 or SDAo/p
0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
From USART0
SI(MO)0 or SDAi/p
To USAET0
0: Input
1: Output
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
55
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.2, input/output with Schmitt-trigger
P3.2/SOMI0
P3IN.2
Pad Logic
EN
D
P3OUT.2
P3DIR.2
P3SEL.2
0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)0
From USART0
(SO)MI0
To USART0
0: Input
1: Output
port P3, P3.3, input/output with Schmitt-trigger
P3.3/UCLK0/SCL
P3IN.3
Pad Logic
EN
D
P3OUT.3
P3DIR.3
P3SEL.3
UCLK.0
0
1
0
1
DCM_UCLK
SYNC
MM
STE
STC
From USART0
UCLK0
To USART0
0: Input
1: Output
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode:
The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
I
2
C, slave mode:
The clock applied to SCL is used to shift data in and out. The frequency of the clock source of the module must be
w
10 times the frequency of the SCL clock.
I
2
C, master mode:
To shift data in and out, the clock is supplied via the SCL terminal to all I
2
C slaves. The frequency of the clock source
of the module must be
w
10 times the frequency of the SCL clock.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
56
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
0
1
1
0
Module X IN
P4IN.x
0: Input
1: Output
Bus
Keeper
Module IN of pin
P5.7/TBOUTH/SVSOUT
x: Bit Identifier, 0 to 6 for Port P4
P4.0/TB0 ...
P4.6/TB6
P4SEL.7
P4DIR.7
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P4Sel.0
P4DIR.0
P4DIR.0
P4OUT.0
Out0 signal
P4IN.0
CCI0A / CCI0B
P4Sel.1
P4DIR.1
P4DIR.1
P4OUT.1
Out1 signal
P4IN.1
CCI1A / CCI1B
P4Sel.2
P4DIR.2
P4DIR.2
P4OUT.2
Out2 signal
P4IN.2
CCI2A / CCI2B
P4Sel.3
P4DIR.3
P4DIR.3
P4OUT.3
Out3 signal
P4IN.3
CCI3A / CCI3B
P4Sel.4
P4DIR.4
P4DIR.4
P4OUT.4
Out4 signal
P4IN.4
CCI4A / CCI4B
P4Sel.5
P4DIR.5
P4DIR.5
P4OUT.5
Out5 signal
P4IN.5
CCI5A / CCI5B
P4Sel.6
P4DIR.6
P4DIR.6
P4OUT.6
Out6 signal
P4IN.6
CCI6A
Signal from Timer_B
Signal to Timer_B
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
57
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4.7/TBCLK
P4IN.7
Timer_B,
Pad Logic
EN
D
P4OUT.7
P4DIR.7
P4SEL.7
0
1
0
1
TBCLK
0: Input
1: Output
DV
SS
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
P5.0/STE1
P5IN.x
Module X IN
Pad Logic
EN
D
P5OUT.x
P5DIR.x
P5SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
x: Bit Identifier, 0 and 4 to 7 for Port P5
0: Input
1: Output
PnSel.x
PnDIR.x
Dir. CONTROL FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P5Sel.0
P5DIR.0
DV
SS
P5OUT.0
DV
SS
P5IN.0
STE.1
P5Sel.4
P5DIR.4
DV
CC
P5OUT.4
MCLK
P5IN.4
unused
P5Sel.5
P5DIR.5
DV
CC
P5OUT.5
SMCLK
P5IN.5
unused
P5Sel.6
P5DIR.6
DV
CC
P5OUT.6
ACLK
P5IN.6
unused
P5Sel.7
P5DIR.7
DV
SS
P5OUT.7
SVSOUT
P5IN.7
TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
58
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5.1/SIMO1
P5IN.1
Pad Logic
EN
D
P5OUT.1
P5DIR.1
P5SEL.1
0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
(SI)MO1
From USART1
SI(MO)1
To USART1
0: Input
1: Output
port P5, P5.2, input/output with Schmitt-trigger
P5.2/SOMI1
P5IN.2
Pad Logic
EN
D
P5OUT.2
P5DIR.2
P5SEL.2
0
1
0
1
DCM_SOMI
SYNC
MM
STE
STC
SO(MI)1
From USART1
(SO)MI1
To USART1
0: Input
1: Output
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
59
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5.3/UCLK1
P5IN.3
Pad Logic
EN
D
P5OUT.3
P5DIR.3
P5SEL.3
0
1
0
1
DCM_SIMO
SYNC
MM
STE
STC
UCLK1
From USART1
UCLK1
To USART1
0: Input
1: Output
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction
is always input.
SPI, slave mode:
The clock applied to UCLK1 is used to shift data in and out.
SPI, master mode:
The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
60
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.5, input/output with Schmitt-trigger
P6IN.x
Module X IN
Pad Logic
EN
D
P6OUT.x
P6DIR.x
P6SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
Bus Keeper
To ADC
From ADC
0: Input
1: Output
x: Bit Identifier, 0 to 5 for Port P6
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0
1 or 1
0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100
A.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
DIR. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DV
SS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DV
SS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DV
SS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DV
SS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DV
SS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DV
SS
P6IN.5
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
61
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt-trigger
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
P6OUT.6
DVSS
P6DIR.6
P6DIR.6
P6SEL.6
D
EN
0
1
1
0
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
P6.6/A6/DAC0
P6IN.6
Pad Logic
0: Input
1: Output
Bus
Keeper
1
0
1, if DAC12.0AMP = 1
'1', if DAC12.0AMP > 0
1, if DAC12.0AMP >1
+
-
INCH = 6
a6
Signal from or to ADC12
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
62
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
0, if DAC12.0CALON = 0 and DAC12.0AMP > 1
P6OUT.7
DVSS
P6DIR.7
P6DIR.7
P6SEL.6
D
EN
0
1
1
0
0: Port Active, T-Switch Off
1: T-Switch On, Port Disabled
P6.7/A7/
P6IN.7
Pad Logic
0: Input
1: Output
Bus
Keeper
1
0
1, if DAC12.0AMP = 1
'1', if DAC12.0AMP > 0
1, if DAC12.0AMP > 1
+
-
INCH = 7
a7
Signal to SVS Block, Selected if VLD = 15
Signal From or To ADC12
VLD Control Bits are Located in SVS
DAC1/SVSIN
To SVS Mux (15)
'1', if VLD = 15
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
63
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDI
TDO
TMS
TCK
Test
JTAG
and
Emulation
Module
Burn & Test
Fuse
Controlled by JTAG
Controlled by JTAG
Controlled
by JTAG
DV
CC
DV
CC
DV
CC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TDO/TDI
TDI/TCLK
TMS
TCK
Fuse
DV
CC
MSP430x15x, MSP430x16x, MSP430x161x
MIXED SIGNAL MICROCONTROLLER
SLAS368D- OCTOBER 2002- REVISED MARCH 2005
64
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I
TF
, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TDI/TCLK
Figure 27. Fuse Check Mode Current, MSP430x15x/16x/161x
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
MSP430F155IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F155IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F156IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F156IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F157IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F157IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1610IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1610IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1610IRTD
ACTIVE
QFN
RTD
64
TBD
Call TI
Call TI
MSP430F1610IRTDR
ACTIVE
QFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1610IRTDT
ACTIVE
QFN
RTD
64
250
Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1611IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1611IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1611IRTD
ACTIVE
QFN
RTD
64
TBD
Call TI
Call TI
MSP430F1611IRTDR
ACTIVE
QFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1611IRTDT
ACTIVE
QFN
RTD
64
250
Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1612IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1612IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1612IRTD
ACTIVE
QFN
RTD
64
TBD
Call TI
Call TI
MSP430F1612IRTDR
ACTIVE
QFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F1612IRTDT
ACTIVE
QFN
RTD
64
250
Green (RoHS &
no Sb/Br)
Level-2-260C-1 YEAR
MSP430F167IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F167IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F168IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F168IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F169IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
MSP430F169IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jul-2005
Addendum-Page 2
MECHANICAL DATA
MTQF008A JANUARY 1995 REVISED DECEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
4040152 / C 11/96
32
17
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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2005, Texas Instruments Incorporated
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