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OPA2680

1997 Burr-Brown Corporation

PDS-1433C

Printed in U.S.A. October, 1999

Dual Wideband, Voltage Feedback

OPERATIONAL AMPLIFIER With Disable

FEATURES

WIDEBAND +5V OPERATION: 220MHz (G = 2)

HIGH OUTPUT CURRENT: 150mA

OUTPUT VOLTAGE SWING:

4.0V

HIGH SLEW RATE: 1800V/

LOW SUPPLY CURRENT: 6.4mA/Ch.

LOW DISABLED CURRENT: 300

A/Ch.

ENABLE/DISABLE TIME: 25ns/100ns

APPLICATIONS

VIDEO LINE DRIVING

xDSL LINE DRIVER/RECEIVER

HIGH SPEED IMAGING CHANNELS

ADC BUFFERS

PORTABLE INSTRUMENTS

TRANSIMPEDANCE AMPLIFIERS

ACTIVE FILTERS

Single-Supply, DC-Coupled, Single-to-Differential ADC Driver

DESCRIPTION

The OPA2680 represents a major step forward in unity
gain stable, voltage feedback op amps. A new internal
architecture provides slew rate and full power band-
width previously found only in wideband current feed-
back op amps. A new output stage architecture delivers
high currents with a minimal headroom requirement.
These combine to give exceptional single supply opera-
tion. Using a single +5V supply, the OPA2680 can
deliver a 1V to 4V output swing with over 100mA drive
current and 150MHz bandwidth. This combination of
features makes the OPA2680 an ideal RGB line driver
or single supply ADC input driver.

The OPA2680's low 6.4mA/ch. supply current is pre-
cisely trimmed at 25

C. This trim, along with low tem-

perature drift, guarantees lower maximum supply current
than competing products. System power may be reduced
further using the optional disable control pin (SO-14
package only). Leaving this disable pin open, or holding
it high, will operate the OPA2680N normally. If pulled
low, the OPA2680N supply current drops to less than
600

A while the output goes into a high impedance state.

1/2

OPA2680

1/2

OPA2680

+5V

0V to +1V

1.5k

1.6k

3.2k

800

400

200

0.1

+3.5V

0.1

+1.5V

+5V

10pF

Clock

0.1

+2.5V

+1.5V

REFT

REFB

ADS822

10-Bit

40MSPS

2.5V

DIFF

OPA2680 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

Voltage Feedback

OPA680

OPA2680

OPA3680

Current Feedback

OPA681

OPA2681

OPA3681

Fixed Gain

OPA682

OPA2682

OPA3682

OPA2680

SBOS086

OPA2680

SPECIFICATIONS: V

= 402

, R

= 100

, and G = +2

(Figure 1 for AC performance only), unless otherwise noted.

OPA2680U, N

TYP

GUARANTEED

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(2)

(3)

+85

(3)

UNITS

MAX

LEVEL

(1)

AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth

G = +1, V

= 0.5Vp-p, R

= 25

400

MHz

typ

G = +2, V

= 0.5Vp-p

220

210

200

190

MHz

min

G = +10, V

= 0.5Vp-p

MHz

min

Gain-Bandwidth Product

300

200

MHz

min

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p

MHz

typ

Peaking at a Gain of +1

< 0.5Vp-p

typ

Large Signal Bandwidth

G = +2, V

= 5Vp-p

175

MHz

typ

Slew Rate

G = +2, 4V Step

1800

1400

1200

900

min

Rise/Fall Time

G = +2, V

= 0.5V Step

1.4

typ

G = +2, V

= 5V Step

2.8

typ

Settling Time to 0.02%

G = +2, V

= 2V Step

typ

0.1%

G = +2, V

= 2V Step

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd Harmonic

= 100

dBc

max

500

dBc

max

3rd Harmonic

= 100

dBc

max

500

dBc

max

Input Voltage Noise

f > 1MHz

4.8

5.3

5.9

6.1

nV/

max

Input Current Noise

f > 1MHz

2.5

2.8

3.0

3.6

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.05

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.03

deg

typ

Channel-to-Channel Crosstalk

f = 5MHz

dBc

typ

DC PERFORMANCE

(4)

Open-Loop Voltage Gain (A

)

= 0V, R

= 100

min

Input Offset Voltage

= 0V

1.0

4.5

5.2

6.0

max

Average Offset Voltage Drift

= 0V

max

Input Bias Current

= 0V

+14

+19

+32

max

Average Bias Current Drift (magnitude)

= 0V

150

nA/

max

Input Offset Current

= 0V

0.1

0.7

1.2

max

Average Offset Current Drift

= 0V

1.5

nA/

max

INPUT
Common-Mode Input Range (CMIR)

(5)

3.5

3.4

3.3

3.2

min

Common-Mode Rejection Ratio (CMRR)

min

Input Impedance

Differential-Mode

= 0

190

|| 0.6

|| pF

typ

Common-Mode

= 0

3.2

|| 0.9

|| pF

typ

OUTPUT
Voltage Output Swing

No Load

4.0

3.8

3.7

3.6

min

100

Load

3.9

3.7

3.6

3.3

min

Current Output, Sourcing

= 0

+190

+160

+140

+80

min

Current Output, Sinking

= 0

150

135

130

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.03

typ

DISABLE (SO-14 Only)

Disabled Low

Power Down Supply Current (+V

)

DIS

= 0, Both Channels

600

typ

Disable Time

100

typ

Enable Time

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

typ

Turn On Glitch

G = +2, R

= 150

, V

= 0

typ

Turn Off Glitch

G = +2, R

= 150

, V

= 0

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (V

DIS

)

DIS

= 0, Each Channel

100

160

160

max

POWER SUPPLY
Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current

12.8

13.6

14.0

14.4

max

Min Quiescent Current

12.8

12.0

12.0

10.6

min

Power Supply Rejection (+PSRR)

Input Referred

min

THERMAL CHARACTERISTICS
Specified Operating Range U, N Package

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

SO-14

100

C/W

typ

NOTES: (1) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

C guaranteed specifications. (3) Junction temperature = ambient at low temperature

limit: junction temperature = ambient +23

C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive-out-of node.

is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA2680

SPECIFICATIONS: V

= +5V

= 402

, R

= 100

to V

/2, G = +2

(Figure 2 for AC performance only), unless otherwise noted.

OPA2680U, N

TYP

GUARANTEED

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(2)

(3)

+85

(3)

UNITS

MAX

LEVEL

(1)

AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth

G = +1, V

< 0.5Vp-p, R

300

MHz

typ

G = +2, V

< 0.5Vp-p

220

120

160

140

MHz

min

G = +10, V

< 0.5Vp-p

MHz

min

Gain-Bandwidth Product

250

200

190

180

MHz

min

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p

MHz

typ

Peaking at a Gain of +1

< 0.5Vp-p

typ

Large Signal Bandwidth

G = +2, V

= 2Vp-p

200

MHz

typ

Slew Rate

G = +2, 2V Step

1000

700

670

550

min

Rise/Fall Time

G = +2, V

= 0.5V Step

1.6

typ

G = +2, V

= 2V Step

2.0

typ

Settling Time to 0.02%

G = +2, V

= 2V Step

typ

0.1%

G = +2, V

= 2V Step

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd Harmonic

= 100

to V

dBc

max

500

to V

dBc

max

3rd Harmonic

= 100

to V

dBc

max

500

to V

dBc

max

Input Voltage Noise

f > 1MHz

5.3

6.0

6.2

nV/

max

Input Current Noise

f > 1MHz

2.5

2.8

3.0

3.4

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150 to V

0.06

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150 to V

0.03

deg

typ

DC PERFORMANCE

(4)

Open-Loop Voltage Gain

= 2.5V, R

= 100

to 2.5V

min

Input Offset Voltage

= 2.5V

2.0

6.0

8.5

max

Average Offset Voltage Drift

= 2.5V

max

Input Bias Current

= 2.5V

+15

+18

+32

max

Average Bias Current Drift (magnitude)

= 2.5V

nA/

max

Input Offset Current

= 2.5V

0.1

0.6

1.0

1.2

max

Average Offset Current Drift

= 2.5V

0.5

1.0

nA/

max

INPUT
Least Positive Input Voltage

(5)

1.5

1.6

1.7

1.8

max

Most Positive Input Voltage

(5)

3.5

3.4

3.3

3.2

min

Common-Mode Rejection Ratio (CMRR)

= 2.5V

0.5V

min

Input Impedance

Differential-Mode

= 2.5V

92 || 1.4

|| pF

typ

Common-Mode

= 2.5V

2.2 || 1.5

|| pF

typ

OUTPUT
Most Positive Output Voltage

No Load

3.8

3.6

3.5

min

= 100

to 2.5V

3.9

3.7

3.5

3.4

min

Least Positive Output Voltage

No Load

1.2

1.4

1.5

max

= 100

to 2.5V

1.1

1.3

1.5

1.7

max

Current Output, Sourcing

+150

+110

+110

+60

min

Current Output, Sinking

110

75

min

Closed-Loop Output Impedance

G =+2, f = 100kHz

0.03

typ

DISABLE (SO-14 Only)

Disabled Low

Power Down Supply Current (+V

)

DIS

= 0, Both Channels

500

typ

Disable Time

100

typ

Enable Time

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

typ

Turn On Glitch

G = +2, R

= 150

, V

= V

typ

Turn Off Glitch

G = +2, R

= 150

, V

= V

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (V

DIS

)

DIS

= 0, Each Channel

100

typ

POWER SUPPLY
Specified Single Supply Operating Voltage

typ

Maximum Single Supply Operating Voltage

max

Max Quiescent Current

= +5V

10.2

12.0

12.0

max

Min Quiescent Current

= +5V

10.2

8.0

8.0

7.6

min

Power Supply Rejection (+PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: U, N

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

SO-14

100

C/W

typ

NOTES: (1) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

C guaranteed specifications. (3) Junction temperature = ambient at low temperature

limit: Junction temperature = ambient +23

C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive-out-of node.

is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA2680

PIN CONFIGURATIONS

Top View

SO-8

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.

ABSOLUTE MAXIMUM RATINGS

Power Supply ..............................................................................

6.5VDC

Internal Power Dissipation ..................................... See Thermal Analysis
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................................

Storage Temperature Range: U, N ................................ 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +175

Out B

In B

+In B

Out A

In A

+In A

SO-14

In A

+In A

DISA

DISB

+In B

In B

Out A

Out B

PACKAGE

SPECIFIED

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

NUMBER

(1)

RANGE

MARKING

NUMBER

(2)

MEDIA

OPA2680U

SO-8 Surface Mount

182

C to +85

OPA2680U

Rails

OPA2680U/2K5

Tape and Reel

OPA2680N

SO-14 Surface mount

235

C to +85

OPA2680N

Rails

OPA2680N/2K5

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "OPA2680U/2K5" will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.

OPA2680

TYPICAL PERFORMANCE CURVES: V

(CONT)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 1.

5MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

2nd Harmonic Distortion (dBc)

= 200

= 500

= 100

5MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

3rd Harmonic Distortion (dBc)

= 200

= 100

= 500

10MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

2nd Harmonic Distortion (dBc)

= 500

= 100

= 200

10MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

3rd Harmonic Distortion (dBc)

= 500

= 100

= 200

20MHz 2nd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

2nd Harmonic Distortion (dBc)

= 500

= 100

= 200

20MHz 3rd HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage Swing (Vp-p)

0.1

3rd Harmonic Distortion (dBc)

= 500

= 100

= 200

OPA2680

TYPICAL PERFORMANCE CURVES: V

(CONT)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 1.

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

2nd Harmonic Distortion (dBc)

= 2Vp-p

= 100

G = +2

G = +10

G = +5

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

3rd Harmonic Distortion (dBc)

= 2Vp-p

= 100

G = +2

G = +10

G = +5

TWO-TONE, 3rd-ORDER SPURIOUS LEVEL

Single-Tone Load Power (dBm)

3rd-Order Spurious Level (dBc)

50MHz

20MHz

10MHz

Load Power at matched 50

load

RECOMMENDED R

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

(

)

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (20MHz/div)

200MHz

100MHz

Gain-to-Capacitive Load (3dB/div)

1/2

OPA2680

402

is optional

= 22pF

= 10pF

G = +2

= 47pF

= 100pF

100

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Frequency (Hz)

100

10k

100k

10M

Voltage Noise (nV/

Hz)

Current Noise (pA/

Hz)

Voltage Noise

Current Noise

2.5pA/

4.8nV/

OPA2680

TYPICAL PERFORMANCE CURVES: V

(CONT)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 1.

100

CMRR AND PSRR vs FREQUENCY

Frequency (Hz)

10k

100M

100k

10M

Power Supply Rejection Ratio (dB)

Common-Mode Rejection Ratio (dB)

PSRR

+PSRR

CMRR

120

150

180

210

240

270

OPEN-LOOP GAIN AND PHASE

Frequency (Hz)

10k

100k

10M

100M

Open-Loop Gain (dB)

Open-Loop Phase (degrees)

Open-Loop Gain

Open-Loop Phase

TYPICAL DC DRIFT OVER TEMPERATURE

Ambient Temperature (°C)

100

120

140

Input Offset Voltage (mV)

Input Bias and Offset Current (µA)

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

(mA)

300

200

100

200

300

(Volts)

100

Load Line

Output Current Limited

1W Internal

Power Limit

One Channel

Only

1W Internal

Power Limit

Output Current Limit

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

COMPOSITE VIDEO dG/dP

Number of 150

Loads

dG/dP (%/degrees)

1/2

OPA2680

402

Optional

1.3k

Pulldown

Video In

+5V

Video

Loads

No Pulldown

With 1.3k

Pulldown

200

150

100

20.0

15.0

10.0

5.0

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Ambient Temperature (°C)

100

120

140

Output Current (50mA/div)

Supply Current (5.0mA/div)

Quiescent Supply Current

Sourcing Output Current

Sinking Output Current

OPA2680

TYPICAL PERFORMANCE CURVES: V

= +5V

At T

= +25

C, G = +2, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 2.

SMALL-SIGNAL FREQUENCY RESPONSE

Frequency (MHz)

Normalized Gain (3dB/div)

0.5

100

500

G = +5

G = +10

G = +2

G = +1

= 25

= 0.5Vp-p

LARGE-SIGNAL FREQUENCY RESPONSE

Frequency (MHz)

0.5

100

500

= 2Vp-p

= 0.5Vp-p

= 1Vp-p

= 3Vp-p

Gain (3dB/div)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (100mV/div)

G = +2

= 0.5Vp-p

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (400mV/div)

G = +2

= 2Vp-p

RECOMMENDED R

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

(

)

Noise Gain = 2.6

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (20MHz/div)

200MHz

100MHz

Gain-to-Capacitive Load (3dB/div)

= 22pF

= 10pF

Signal Gain = +2
Noise Gain = 2.6

= 47pF

= 100pF

1/2

OPA2680

402

714

+5V

0.1µF

OPA2680

TYPICAL PERFORMANCE CURVES: V

= +5V

At T

= +25

C, G = +2, R

= 402

, and R

= 100

, unless otherwise noted. See Figure 2.

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

2nd Harmonic Distortion (dBc)

= 2Vp-p

= 100

to V

G = +2

G = +10

G = +5

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

3rd Harmonic Distortion (dBc)

= 2Vp-p

= 100

to V

G = +2

G = +10

G = +5

2nd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

2nd Harmonic Distortion (dBc)

= 500

= 200

= 100

= 2Vp-p

3rd HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.1

3rd Harmonic Distortion (dBc)

= 500

= 100

= 2Vp-p

= 200

0.1

0.01

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Frequency (Hz)

10k

100M

100k

10M

Output Impedance (

)

1/2

OPA2680

402

+5V

402

200

TWO-TONE, 3RD-ORDER SPURIOUS LEVEL

Single-Tone Load Power (dBm)

3rd-Order Spurious Level (dBc)

50MHz

10MHz

Load Power at Matched 50

Load

20MHz

dBc = dB Below Carrier

OPA2680

APPLICATIONS INFORMATION

WIDEBAND VOLTAGE FEEDBACK OPERATION

The OPA2680 provides an exceptional combination of high
output power capability in a dual, wideband, unity gain
stable voltage feedback op amp using a new high slew rate
input stage. Typical differential input stages used for voltage
feedback op amps are designed to steer a fixed-bias current
to the compensation capacitor, setting a limit to the achiev-
able slew rate. The OPA2680 uses a new input stage which
places the transconductance element between two input
buffers, using their output currents as the forward signal. As
the error voltage increases across the two inputs, an increas-
ing current is delivered to the compensation capacitor. This
provides very high slew rate (1800V/

s) while consuming

relatively low quiescent current (6.4mA/ch.). This excep-
tional full power performance comes at the price of a slightly
higher input noise voltage than alternative architectures. The
4.8nV/

Hz input voltage noise for the OPA2680 is excep-

tionally low for this type of input stage.

Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the

Specifications and Typical Performance Curves. This is for
one channel. The other channel is connected similarly. For
test purposes, the input impedance is set to 50

with a

resistor to ground and the output impedance is set to 50

with a series output resistor. Voltage swings reported in the
specifications are taken directly at the input and output pins,
while output powers (dBm) are at the matched 50

load. For

the circuit of Figure 1, the total effective load will be 100

|| 804

. The disable control line (SO-14 package only) is

typically left open to guarantee normal amplifier operation.
Two optional components are included in Figure 1. An
additional resistor (175

) is included in series with the non-

inverting input. Combined with the 25

DC source resis-

tance looking back towards the signal generator, this gives an
input bias current cancelling resistance that matches the

200

source resistance seen at the inverting input (see the

DC Accuracy and Offset Control section). In addition to the
usual power supply decoupling capacitors to ground, a 0.1

capacitor is included between the two power supply pins. In
practical PC board layouts, this optional-added capacitor will
typically improve the 2nd harmonic distortion performance
by 3dB to 6dB.

Figure 2 shows the AC-coupled, gain of +2, single supply
circuit configuration which is the basis of the +5V Specifi-
cations and Typical Performance Curves. Though not a "rail-
to-rail" design, the OPA2680 requires minimal input and
output voltage headroom compared to other very wideband
voltage feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with >150MHz bandwidth.
The key requirement of broadband single-supply operation is
to maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 2 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 698

resistors).

Separate networks would be required at each input. The
input signal is then AC-coupled into the midpoint voltage
bias. The input voltage can swing to within 1.5V of either
supply pin, giving a 2Vp-p input signal range centered
between the supply pins. The input impedance matching
resistor (59

) used for testing is adjusted to give a 50

input

load when the parallel combination of the biasing divider
network is included. Again, an additional resistor (50

this case) is included directly in series with the non-inverting
input. This minimum recommended value provides part of
the DC source resistance matching for the non-inverting
input bias current. It is also used to form a simple parasitic
pole to roll off the frequency response at very high frequen-
cies (>500MHz) using the input parasitic capacitance. The
gain resistor (R

) is AC-coupled, giving the circuit a DC

gain of +1, which puts the input DC bias voltage (2.5V) on
the output as well. The output voltage can swing to within
1V of either supply pin while delivering >100mA output

FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-

cation and Test Circuit.

FIGURE 2. AC-Coupled, G = +2, Single Supply Specifica-

tion and Test Circuit.

1/2

OPA2680

+5V

DIS

Load

175

Source

402

6.8µF

0.1µF

6.8µF

0.1µF

1/2

OPA2680

+5V

DIS

698

100

698

402

0.1µF

6.8µF

0.1µF

OPA2680

current. A demanding 100

load to a midpoint bias is used

in this characterization circuit. The new output stage circuit
used in the OPA2680 can deliver large bipolar output cur-
rents into this midpoint load with minimal crossover distor-
tion, as shown in the +5V supply, 3rd harmonic distortion
plots.

SINGLE SUPPLY A/D CONVERTER INTERFACE

Most modern, high performance analog-to-digital convert-
ers (such as the Burr-Brown ADS8xx and ADS9xx series)
operate on a single +5V (or lower) power supply. It has been
a considerable challenge for single supply op amps to
deliver a low distortion input signal at the ADC input for
signal frequencies exceeding 5MHz. The high slew rate,
exceptional output swing and high linearity of the OPA2680
make it an ideal single supply ADC driver. The circuit on the
front page shows one possible interface particularly suited to
DC-coupled pulse digitization requirements. Figure 3 shows
the AC-coupled test circuit of Figure 2 modified for a
capacitive (A/D) load and with an optional output pull-down
resistor (R

The OPA2680 in the circuit of Figure 3 provides >200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd harmonic
distortion or two-tone, 3rd-order intermodulation distortion
will be observed due to the very low crossover distortion in
the OPA2680 output stage. The limit of output Spurious
Free Dynamic Range (SFDR) will be set by the 2nd har-
monic distortion. Without R

, the circuit of Figure 3 mea-

sured at 10MHz shows an SFDR of 65dBc. This may be
improved by pulling additional DC bias current (I

) out of

the output stage through the optional R

resistor to ground

(the output midpoint is at 2.5V for Figure 3). Adjusting I

gives the improvement in SFDR shown in Figure 4. SFDR
improvement is achieved for I

values up to 6mA, with

worse performance for higher values. Using the dual
OPA2680 in an IQ receiver channel will give matched AC
performance through high frequencies.

FIGURE 4. SFDR vs I

Output Pull-Down Current (mA)

SFDR (dBc)

= 2Vp-p, 10MHz

HIGH PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER

High frequency DDS DACs require a low distortion output
amplifier to retain their SFDR performance into real-world
loads. A differential output drive implementation is shown
in Figure 5. The diagram shows the signal output current(s)
connected into the virtual ground summing junction(s) of
the OPA2680, which is set up as a transimpedance stage or
"I-V converter". If the DAC requires its outputs terminated
to a compliance voltage other than ground for operation,
the appropriate voltage level may be applied to the non-
inverting inputs of the OPA2680. The DC gain for this
circuit is equal to R

. At high frequencies, the DAC output

capacitance (C

in Figure 5) will produce a zero in the

noise gain for the OPA2680 that may cause peaking in the
closed-loop frequency response. C

is added across R

compensate for this noise gain peaking. To achieve a flat

FIGURE 3. Single-Supply ADC Input Driver. One of Two Channels.

1/2

OPA2680

402

1Vp-p

698

+5V

0.1µF

50pF

0.1µF

2.5V DC
±1V AC

ADC Input

Power supply decoupling not shown

OPA2680

transimpedance frequency response, the pole in each feed-
back network should be set to:

1/2

GBP/4

which will give a corner frequency f

3dB

of approximately:

3dB

GBP/(2

)

WIDEBAND VIDEO MULTIPLEXING

One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple "Wired-OR
Video Multiplexer" can be easily implemented using the
OP2680N (SO-14 package only) as shown in Figure 6.

Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approxi-
mately equal at this time. The "make-before-break" disable
characteristic of the OPA2680N ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that shown in Figure 6. Since both inputs may be
on for a short period during the transition between channels,
the outputs are combined through the output impedance
matching resistors (82.5

in this case). When one channel is

disabled, its feedback network forms part of the output
impedance and slightly attenuates the signal in getting out
onto the cable. The gain and output matching resistor have
been slightly increased to get a signal gain of +1 at the
matched load and provide a 75

output impedance to the

cable. The video multiplexer connection (Figure 6) also
insures that the maximum differential voltage across the
inputs of the unselected channel does not exceed the rated

1.2V maximum for standard video signal levels.

The section on Disable Operation shows the turn-on and
turn-off switching glitches using a 0V input for a single
channel is typically less than

50mV. Where two outputs are

switched (as shown in Figure 6), the output line is always
under the control of one amplifier or the other due to the
"make-before-break" disable timing. In this case, the switch-
ing glitches for two 0V inputs drop to <20mV.

FIGURE 6. Two-Channel Video Multiplexer (SO-14 package only).

FIGURE 5. High Speed DAC--Differential Transimpedance

Amplifier

1/2

OPA2680

1/2

OPA2680

High Speed

DAC

= I

GBP

Gain Bandwidth

Product (Hz) for the OPA2680

82.5

Cable

Load

RG-59

82.5

402

340

Video 1

+5V

1/2

OPA2680

1/2

OPA2680

402

340

Video 2

+5V

DIS

DISA

DISB

OPA2680

HIGH SPEED DELAY CIRCUIT

The OPA2680 makes an ideal amplifier for a variety of
active filter designs. Shown in Figure 7 is a circuit that
utilizes the two amplifiers within the dual OPA2680 to
design a two-stage analog group delay adjustment circuit.
For simplicity, the circuit assumes a dual supply (

5V)

operation, but it can also be modified to operate on signal
supply. The input to the first filter stage is driven by the
wideband buffer amplifier, BUF601 to isolate the signal
input from the filter network. The BUF601 features an open-
loop design, holding its output impedance at 4

for frequen-

cies in excess of 200MHz.

Each of the two filter stages is a 1st-order filter with a
voltage gain of +1. The delay time through one filter is given
by Equation 1.

Equation 1:

GR0

= 2RC

For a more accurate analysis of the circuit consider the group
delay for the amplifiers. For example, in the case of the
OPA2680, the group delay in the bandwidth from 1MHz to
100MHz is approximately 1.0ns. To account for this, modify
the transfer function, which now comes out to be:

Equation 2:

= 2 (2RC +T

)

with T

= (1/360) · (d

/df) = delay of the op amp itself. The

values of resistors R

and R

should be equal and low to

avoid parasitic effects. If the all-pass filter is designed for
very low delay times, include parasitic board capacitances
to calculate the correct delay time. Simulating this applica-
tion using the PSPICE model of the OPA2680 will allow this
design to be tuned.

DIFFERENTIAL RECEIVER/DRIVER

A very versatile application for a dual operational amplier
is the differential amplifier configuration shown in Figure
8. With both amplifiers of the OPA2680 connected for
non-inverting operation, the circuit provides a high input
impedance while the gain can easily be set by just one
resistor, R

. When operated in low gains, the output swing

may be limited as a result of the common-mode input
swing limits of the amplifier itself. An interesting modifi-
cation of this circuit is to place a capacitor in series with
the R

. Now the DC gain for each side is reduced to +1,

while the AC gain still follows the standard transfer func-
tion of G = 1 + 2R

. This might be advantageous for

applications processing only a frequency band which ex-
cludes DC or very low frequencies. An input DC voltage
resulting from input bias currents will not be amplified by
the AC gain and can be kept low. This circuit can be used
as a differential line receiver, driver, or as an interface to
a differential input A/D converter.

FIGURE 7. Two Stage, All-Pass Network.

FIGURE 8. High Speed Differential Receiver.

402

OUT

1/2

OPA2680

BUF601

1/2

OPA2680

402

1/2

OPA2680

1/2

OPA2680

DIFF

= 1 +

OPA2680

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Several PC boards are available to assist in the initial evalu-
ation of circuit performance using the OPA2680 in its two
package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documenta-
tion. The summary information for these boards is shown
below:

A good rule of thumb is to target the parallel combination of
R

and R

(Figure 1) to be less than approximately 300

The combined impedance R

|| R

interacts with the invert-

ing input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 2pF total parasitic on the inverting node, hold-
ing R

|| R

< 300

will keep this pole above 250MHz. By

itself, this constraint implies that the feedback resistor R

can increase to several k

at high gains. This is acceptable

as long as the pole formed by R

and any parasitic capaci-

tance appearing in parallel is kept out of the frequency range
of interest.

BANDWIDTH VS GAIN: NON-INVERTING OPERATION

Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90

, as it

does in high gain configurations. At low gains (increased
feedback factor), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA2680 is
compensated to give a slightly peaked response in a non-
inverting gain of 2 (Figure 1). This results in a typical gain
of +2 bandwidth of 220MHz, far exceeding that predicted by
dividing the 300MHz GBP by 2. Increasing the gain will
cause the phase margin to approach 90

and the bandwidth

to more closely approach the predicted value of (GBP/NG).
At a gain of +10, the 30MHz bandwidth shown in the
Typical Specifications agrees with that predicted using the
simple formula and the typical GBP of 300MHz.

The frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2
signal gain, is to add an 804

resistor across the two inputs

in the circuit of Figure 1. A similar technique may be used
to reduce peaking in unity gain (voltage follower) applica-
tions. For example, by using a 402

feedback resistor along

with a 402

resistor across the two op amp inputs, the

voltage follower response will be similar to the gain of +2
response of Figure 2. Reducing the value of the resistor
across the op amp inputs will further limit the frequency
response due to increased noise gain.

The OPA2680 exhibits minimal bandwidth reduction going
to single supply (+5V) operation as compared with

5V.

This is because the internal bias control circuitry retains
nearly constant quiescent current as the total supply voltage
between the supply pins is changed.

INVERTING AMPLIFIER OPERATION

Since the OPA2680 is a general purpose, wideband volt-
age feedback op amp, all of the familiar op amp applica-
tion circuits are available to the designer. Inverting opera-
tion is one of the more common requirements and offers

BOARD

PART

ORDERING

PRODUCT

PACKAGE

NUMBER

OPA2680U

8-Lead SO-8

DEM-OPA26xU

MKT-352

OPA2680N

SO-14

DEM-OPA26xN

MKT-353

Contact the Burr-Brown Applications support line to request
any of these boards.

MACROMODELS AND APPLICATIONS SUPPORT

Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA2680 is available through either
the Burr-Brown Internet web page (http://www.burr-
brown.com) or as one model on a disk from the Burr-Brown
Applications Department (1-800-548-6132). The Applica-
tion Department is also available for design assistance at this
number. These models do a good job of predicting small-
signal AC and transient performance under a wide variety of
operating conditions. They do not do as well in predicting
the harmonic distortion or dG/dP characteristics. These
models do not attempt to distinguish between the package
types in their small-signal AC performance.

OPERATING SUGGESTIONS

OPTIMIZING RESISTOR VALUES

Since the OPA2680 is a unity gain stable voltage feedback
op amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 25

resistor, not a direct short. This

will isolate the inverting input capacitance from the output
pin and improve the frequency response flatness. Usually,
the feedback resistor value should be between 200

and

1.5k

. Below 200

, the feedback network will present

additional output loading which can degrade the harmonic
distortion performance of the OPA2680. Above 1.5k

, the

typical parasitic capacitance (approximately 0.2pF) across
the feedback resistor may cause unintentional band-limiting
in the amplifier response.

OPA2680

several performance benefits. Figure 9 shows a typical
inverting configuration where the I/O impedances and
signal gain from Figure 1 are retained in an inverting
circuit configuration.

ance is added in series with R

for calculating the noise gain

(NG). The resultant NG is 2.8 for Figure 9, as opposed to only
2 if R

could be eliminated as discussed above. The band-

width will therefore be slightly lower for the gain of 2 circuit
of Figure 9 than for the gain of +2 circuit of Figure 1.

The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor on the
non-inverting input (R

). If this resistor is set equal to the

total DC resistance looking out of the inverting node, the
output DC error, due to the input bias currents, will be
reduced to (Input Offset Current) · R

. If the 50

source

impedance is DC-coupled in Figure 9, the total resistance to
ground on the inverting input will be 228

. Combining this

in parallel with the feedback resistor gives the R

= 146

used in this example. To reduce the additional high fre-
quency noise introduced by this resistor, it is sometimes
bypassed with a capacitor. As long as R

<350

, the

capacitor is not required since the total noise contribution of
all other terms will be less than that of the op amp's input
noise voltage. As a minimum, the OPA2680 requires an R

value of 50

to damp out parasitic-induced peaking--a

direct short to ground on the non-inverting input runs the
risk of a very high frequency instability in the input stage.

OUTPUT CURRENT AND VOLTAGE

The OPA2680 provides output voltage and current capabili-
ties that are unsurpassed in a low cost monolithic op amp.
Under no-load conditions at +25

C, the output voltage

typically swings closer than 1V to either supply rail; the
guaranteed swing limit is within 1.2V of either rail. Into a
15

load (the minimum tested load), it is guaranteed to

deliver more than

135mA.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Performance Curves. The X and Y axes of this graph show
the zero-voltage output current limit and the zero-current
output voltage limit, respectively. The four quadrants give a
more detailed view of the OPA2680's output drive capabili-
ties, noting that the graph is bounded by a "Safe Operating
Area" of 1W maximum internal power dissipation for each
channel separately. Superimposing resistor load lines onto
the plot shows that the OPA2680 can drive

2.5V into 25

3.5V into 50

without exceeding the output capabilities

or the 1W dissipation limit. A 100

load line (the standard

test circuit load) shows the full

3.9V output swing capabil-

ity, as shown in the typical specifications.

The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V

's (increasing the available output voltage swing) and

increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output

1/2

OPA2680

402

200

146

Source

+5V

0.1

6.8

0.1

6.8

Load

= 2

FIGURE 9. Gain of 2 Example Circuit.

In the inverting configuration, three key design consider-
ation must be noted. The first is that the gain resistor (R

)

becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), R

may be set equal to the required termination value and R

adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R

for input matching eliminates the need for R

but

requires a 100

feedback resistor. This has the interesting

advantage that the noise gain becomes equal to 2 for a 50

source impedance--the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100

feedback resistor in parallel with the external

load. In general, the feedback resistor should be limited to
the 200

to 1.5k

range. In this case, it is preferable to

increase both the R

and R

values as shown in Figure 8, and

then achieve the input matching impedance with a third
resistor (R

) to ground. The total input impedance becomes

the parallel combination of R

and R

The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes part
of the noise gain equation and influences the bandwidth. For
the example in Figure 9, the R

value combines in parallel

with the external 50

source impedance, yielding an effec-

tive driving impedance of 50

|| 67

= 28.6

. This imped-

OPA2680

voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.

To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pin (8-pin packages) will, in
most cases, destroy the amplifier. Including a small series
resistor (5

) in the power supply line will protect against

this. Always place the 0.1

F decoupling capacitor directly

on the supply pins.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter--including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA2680 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the amplifier's open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop re-
sponse, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.

The Typical Performance Curves show the recommended
R

versus capacitive load and the resulting frequency re-

sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA2680.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always con-
sider this effect carefully, and add the recommended series
resistor as close as possible to the OPA2680 output pin (see
Board Layout Guidelines).

The criterion for setting this R

resistor is a maximum

bandwidth, flat frequency response at the load. For the
OPA2680 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of R

flatten the response at the load. Increasing the noise gain will
reduce the peaking as described previously. The circuit of
Figure 10 demonstrates this technique, allowing lower val-
ues of R

to be used for a given capacitive load.

100

Capacitive Load (pF)

100

Series Resistor, R

(

)

NG = 2

NG = 3

NG = 4

FIGURE 11. Required R

vs Noise Gain.

This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing
the unloaded phase margin for the op amp. Although this
technique will reduce the required R

resistor for a given

capacitive load, it does increase the noise at the output. It
also will decrease the loop gain, nominally decreasing the
distortion performance. If, however, the dominant distortion
mechanism arises from a high R

value, significant dynamic

range improvement can be achieved using this technique.
Figure 11 shows the required R

versus C

LOAD

parametric on

noise gain using this technique. This is the circuit of Figure
10 with R

adjusted to increase the noise gain (increasing

the phase margin) then sweeping C

LOAD

and finding the

required R

to get a flat frequency response. This plot also

gives the required R

versus C

LOAD

for the OPA2680 oper-

ated at higher signal gains.

DISTORTION PERFORMANCE

The OPA2680 provides good distortion performance into a
100

load on

5V supplies. Relative to alternative solu-

tions, it provides exceptional performance into lighter loads
and/or operating on a single +5V supply. Generally, until
the fundamental signal reaches very high frequency or
power levels, the 2nd harmonic will dominate the distortion
with a negligible 3rd harmonic component. Focusing then
on the 2nd harmonic, increasing the load impedance im-

FIGURE 10. Capacitive Load Driving with Noise Gain Tuning.

1/2

OPA2680

402

175

402

+5V

LOAD

Power supply decoupling

not shown.

OPA2680

proves distortion directly. Remember that the total load
includes the feedback network; in the non-inverting configu-
ration (Figure 1) this is sum of R

+ R

, while in the

inverting configuration, it is just R

. Also, providing an

additional supply decoupling capacitor (0.1

F) between the

supply pins (for bipolar operation) improves the 2nd-order
distortion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The new output stage
used in the OPA2680 actually holds the difference between
fundamental power and the 2nd and 3rd harmonic powers
relatively constant with increasing output power until very
large output swings are required (>4Vp-p). This also shows
up in the two-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues
to hold them low even as the fundamental power reaches
very high levels. As the Typical Performance Curves show,
the spurious intermodulation powers do not increase as
predicted by a traditional intercept model. As the fundamen-
tal power level increases, the dynamic range does not de-
crease significantly. For 2 tones centered at 20MHz, with
10dBm/tone into a matched 50

load (i.e., 2Vp-p for each

tone at the load, which requires 8Vp-p for the overall two-
tone envelope at the output pin), the Typical Performance
Curves show 57dBc difference between the test tone powers
and the 3rd-order intermodulation spurious powers. This
exceptional performance improves further when operating at
lower frequencies.

NOISE PERFORMANCE

High slew rate, unity gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 4.8nV/

Hz input voltage noise for

the OPA2680 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 12 shows the op amp noise analysis model with all
the noise terms included. In this model, all noise terms are
taken to be noise voltage or current density terms in either
nV/

Hz or pA/

Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 12.

Equation 3:

Dividing this expression by the noise gain (NG = (1+R

))

will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 4.

Equation 4:

Evaluating these two equations for the OPA2680 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 11nV/

Hz and a total equivalent input

spot noise voltage of 5.5nV/

Hz. This is including the noise

added by the bias current cancellation resistor (175

) on the

non-inverting input. This total input-referred spot noise
voltage is only slightly higher than the 4.8nV/

Hz specifica-

tion for the op amp voltage noise alone. This will be the case
as long as the impedances appearing at each op amp input
are limited to the previously recommend maximum value of
300

. Keeping both (R

|| R

) and the non-inverting input

source impedance less than 300

will satisfy both noise and

frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capaci-
tive decoupling across the bias current cancellation resistor
(R

) for the inverting op amp configuration of Figure 9 is not

required.

DC ACCURACY AND OFFSET CONTROL

The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA2680
gives even tighter control than comparable amplifiers. Al-
though the high speed input stage does require relatively
high input bias current (typically 14

A out of each input

terminal), the close matching between them may be used to
reduce the output DC error caused by this current. The total
output offset voltage may be considerably reduced by match-
ing the DC source resistances appearing at the two inputs.
This reduces the output DC error due to the input bias
currents to the offset current times the feedback resistor.
Evaluating the configuration of Figure 1, using worst-case
+25

C input offset voltage and current specifications, gives

a worst-case output offset voltage equal to:

(NG · V

OS(MAX)

)

· I

OS(MAX)

)

(2 · 4.5mV)

(402

· 0.7

9.3mV

(NG = non-inverting signal gain)

4kT

1/2

OPA2680

4kT = 1.6E 20J

at 290°K

4kTR

FIGURE 12. Op Amp Noise Analysis Model.

(

)

+ 4

kTR

+ 4

kTR

(

)

+ 4

kTR

(

)

(

)

+ 4

kTR

OPA2680

A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques eventually reduce to add-
ing a DC current through the feedback resistor. In selecting
an offset trim method, one key consideration is the impact
on the desired signal path frequency response. If the signal
path is intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. However, the DC offset voltage on
the summing junction will set up a DC current back into the
source which must be considered. Applying an offset adjust-
ment to the inverting op amp input can change the noise gain
and frequency response flatness. For a DC-coupled invert-
ing amplifier, Figure 13 shows one example of an offset
adjustment technique that has minimal impact on the signal
frequency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.

eventually turning on those two diodes (

100uA). At this

point, any further current pulled out of V

DIS

goes through

those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode are only those required to operate the
circuit of Figure 14. Additional circuitry ensures that turn-on
time occurs faster than turn-off time (make-before-break).

When disabled, the output and input nodes go to a high
impedance state. If the OPA2680 is operating in a gain of
+1, this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (R

+ R

) will

appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input
and output will be connected through the feedback network
resistance (R

+ R

) and the isolation will be very poor as a

result.

One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 15
shows these glitches for the circuit of Figure 1 with the input
signal at 0V. The glitch waveform at the output pin is plotted
along with the DIS pin voltage.

±200mV Output Adjustment

= = 2

Supply Decoupling

Not Shown

328

0.1µF

500

20k

10k

0.1µF

+5V

1/2

OPA2680

+5V

FIGURE 13. DC-Coupled, Inverting Gain of 2, with Offset

Adjustment.

25k

110k

15k

Control

DIS

FIGURE 14. Simplified Disable Control Circuit.

Time (20ns/div)

Output Voltage (20mV/div)

Output Voltage

(0V Input)

DIS

0.2V

4.8V

FIGURE 15. Disable/Enable Glitch.

DISABLE OPERATION (SO-14 Package Only)

The OPA2680N provides an optional disable feature that
may be used either to reduce system power or to implement
a simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA2680N will operate nor-
mally. To disable, the control pin must be asserted LOW.
Figure 14 shows a simplified internal circuit for the disable
control feature.

In normal operation, base current to Q1 is provided through
the 110k

resistor, while the emitter current through the

15k

resistor sets up a voltage drop that is inadequate to

turn on the two diodes in Q1's emitter. As V

DIS

is pulled

LOW, additional current is pulled through the 15k

resistor

OPA2680

The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 15, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 2k

series resistor between the

logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring adequate logic level swing.

THERMAL ANALYSIS

Due to the high output power capability of the OPA2680,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in

the output stage (P

) to deliver load power. Quiescent

power is simply the specified no-load supply current times
the total supply voltage across the part. P

will depend on

the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P

= V

/(4·R

)

where R

includes feedback network loading.

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As a worst-case example, compute the maximum T

using an

OPA2680U (SO-8 package) in the circuit of Figure 1 operat-
ing at the maximum specified ambient temperature of +85

and with both outputs driving a grounded 20

load to +2.5V.

= 10V · 14.4mA + 2 [5

/(4·(20

|| 804

))] = 785mW

Maximum T

= +85

C + (0.79W · 125

C/W) = 184

This absolute worst-case condition exceeds the specified
maximum junction temperature. Actual P

will always be

less than that considered here. Carefully consider maximum
T

in your application.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high frequency
amplifier like the OPA2680 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be

opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.

b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1

F decoupling capacitors. At the

device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1

F) across

the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2

F to 6.8

decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.

c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA2680. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition axially-
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board traces as
short as possible. Never use wirewound type resistors in a
high frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values >1.5k

this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor
values as low as possible consistent with load driving con-
siderations. The 402

feedback used in the typical perfor-

mance specifications is a good starting point for design.
Note that a 25

feedback resistor, rather than a direct short,

is suggested for the unity gain follower application. This
effectively isolates the inverting input capacitance from the
output pin that would otherwise cause additional peaking in
the gain of +1 frequency response.

d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R

from the

plot of Recommended R

vs Capacitive Load. Low parasitic

capacitive loads (<5pF) may not need an R

since the

OPA2680

OPA2680 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
R

are allowed as the signal gain increases (increasing the

unloaded phase margin) If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50

environment is normally not necessary

on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA2680
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA2680 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly terminated transmission line is unacceptable, a
long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of Recommended
R

vs Capacitive Load. This will not preserve signal integ-

rity as well as a doubly terminated line. If the input imped-
ance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.

e) Socketing a high speed part like the OPA2680 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA2680
onto the board.

FIGURE 16. Internal ESD Protection.

External

Internal
Circuitry

INPUT AND ESD PROTECTION

The OPA2680 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins are protected with
internal ESD protection diodes to the power supplies as
shown in Figure 16.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with

15V supply

parts driving into the OPA2680), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.

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