Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- OPA690 RELATED PRODUCTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE/ORDERING INFORMATION
- DEVICE INFORMATION
- ELECTRICAL CHARACTERISTICS: Vs=+/-5V
- TYPICAL CHARACTERISTICS: Vs=+/-5V
- TYPICAL CHARACTERISTICS: Vs=+5V
- APPLICATIONS INFORMATION
- WIDEBAND VOLTAGE FEEDBACK OPERATION
- SINGLE-SUPPLY ADC INTERFACE
- HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER
- HIGH POWER LINE DRIVER
- SINGLE-SUPPLY ACTIVE FILTERS
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- OPTIMIZING RESISTOR VALUES
- BANDWIDTH VERSUS GAIN: NONINVERTING OPERATION
- INVERTING AMPLIFIER OPERATION
- OUTPUT CURRENT AND VOLTAGE
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- NOISE PERFORMANCE
- DC ACCURACY AND OFFSET CONTROL
- DISABLE OPERATION
- THERMAL ANALYSIS
- BOARD LAYOUT GUIDELINES
- PACKAGE DRAWINGS
- D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE
Wideband, Voltage Feedback
OPERATIONAL AMPLIFIER With Disable
FEATURES
q
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
2.5V to
5V Dual Supply
q
UNITY-GAIN STABLE: 500MHz (G = 1)
q
HIGH OUTPUT CURRENT: 190mA
q
OUTPUT VOLTAGE SWING:
4.0V
q
HIGH SLEW RATE: 1800V/
s
q
LOW SUPPLY CURRENT: 5.5mA
q
LOW DISABLED CURRENT: 100
A
q
WIDEBAND +5V OPERATION: 220MHz (G = 2)
APPLICATIONS
q
VIDEO LINE DRIVER
q
xDSL LINE DRIVER/RECEIVER
q
HIGH SPEED IMAGING CHANNELS
q
ADC BUFFERS
q
PORTABLE INSTRUMENTS
q
TRANSIMPEDANCE AMPLIFIERS
q
ACTIVE FILTERS
q
OPA680 UPGRADE
DESCRIPTION
The OPA690 represents a major step forward in unity-gain
stable, voltage feedback op amps. A new internal architec-
ture provides slew rate and full-power bandwidth previously
found only in wideband current feedback op amps. A new
output stage architecture delivers high currents with a
minimal headroom requirement. These combine to give
exceptional single-supply operation. Using a single +5V
supply, the OPA690 can deliver a 1V to 4V output swing
with over 150mA drive current and 150MHz bandwidth.
This combination of features makes the OPA690 an ideal
RGB line driver or single-supply Analog-to-Digital Con-
verter (ADC) input driver.
The OPA690's low 5.5mA supply current is precisely trimmed
at 25
C. This trim, along with low temperature drift, gives
lower maximum supply current than competing products.
System power may be reduced further using the optional
disable control pin. Leaving this disable pin open, or holding
it HIGH, will operate the OPA690 normally. If pulled LOW,
the OPA690 supply current drops to less than 100
A while
the output goes to a high impedance state. This feature may
be used for power savings.
OPA690 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
OPA680
OPA2690
OPA3690
Current Feedback
OPA691
OPA2691
OPA3691
Fixed Gain
OPA692
OPA2682
OPA3692
OPA690
SBOS223A--DECEMBER 2001 REVISED JULY 2002
www.ti.com
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OPA6
90
OPA6
90
R
4
20
R
5
20
C
3
20pF
C
6
20pF
C
4
10
F
C
5
0.1
F
THS1040
10-Bit
40MSPS
AIN+
AIN
V
REF
= 1V
C
2
8
OPA690
3
2
4
R
1
+5V
R
2
R
1
R
3
0.1
F
2.5V
C
1
V
I
3.3V
Single-Supply ADC Driver
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OPA690
2
SBOS223A
www.ti.com
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA690ID
SO-8
D
40
C to +85
C
OPA690
OPA690ID
Rails, 100
"
"
"
"
"
OPA690IDR
Tape and Reel, 2500
OPA690IDBV
SOT23-6
DBV
40
C to +85
C
OAEI
OPA690IDBVT
Tape and Reel, 250
"
"
"
"
"
OPA690IDBVR
Tape and Reel, 3000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
1
2
3
4
8
7
6
5
NC
Inverting Input
Noninverting Input
V
S
DIS
+V
S
Output
NC
PIN CONFIGURATIONS
Top View
SO
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ...............................................................................
6.5V
DC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ...........................................................................
V
S
Storage Temperature Range: D, DBV ........................... 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +175
C
ESD Resistance: HBM .................................................................... 2000V
MM ........................................................................ 200V
CDM .................................................................... 1500V
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
Top View
SOT23
PACKAGE/ORDERING INFORMATION
1
2
3
6
5
4
Output
V
S
Noninverting Input
+V
S
DIS
Inverting Input
OAEI
1
2
3
6
5
4
Pin Orientation/Package Marking
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
OPA690
3
SBOS223A
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
R
F
= 402
, R
L
= 100
, and G = +2
,
(see Figure 1 for AC performance only), unless otherwise noted.
OPA690ID, IDBV
TYP
MIN /MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
G = +1, V
O
= 0.5Vp-p, R
F
= 25
500
MHz
typ
C
G = +2, V
O
= 0.5Vp-p
220
165
160
150
MHz
typ
C
G = +10, V
O
= 0.5Vp-p
30
20
19
18
MHz
typ
C
Gain-Bandwidth Product
G
10
300
200
190
180
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
30
MHz
typ
C
Peaking at a Gain of +1
V
O
< 0.5Vp-p
4
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 5Vp-p
200
MHz
typ
C
Slew Rate
G = +2, 4V Step
1800
1400
1200
900
V/
s
typ
C
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
1.4
ns
typ
C
G = +2, V
O
= 5V Step
2.8
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
68
64
62
60
dBc
typ
C
R
L
500
77
70
68
66
dBc
typ
C
3rd-Harmonic
R
L
= 100
70
68
66
64
dBc
typ
C
R
L
500
81
78
76
75
dBc
typ
C
Input Voltage Noise
f > 1MHz
5.5
nV/
Hz
typ
C
Input Current Noise
f > 1MHz
3.1
pA/
Hz
typ
C
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.06
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.03
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V, R
L
= 100
69
58
56
54
dB
min
A
Input Offset Voltage
V
CM
= 0V
1.0
4
4.5
4.7
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
10
10
V/
C
max
B
Input Bias Current
V
CM
= 0V
+3
8
9
11
A
max
A
Average Bias Current Drift (magnitude)
V
CM
= 0V
20
40
nA/
C
max
B
Input Offset Current
V
CM
= 0V
0.1
1.0
1.4
1.6
A
max
A
Average Offset Current Drift
V
CM
= 0V
7
9
nA/
C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
=
1V
65
60
57
56
dB
min
A
Input Impedance
Differential-Mode
V
CM
= 0
190 || 0.6
k
|| pF
typ
C
Common-Mode
V
CM
= 0
3.2 || 0.9
M
|| pF
typ
C
OUTPUT
Voltage Output Swing
No Load
4.0
3.8
3.7
3.6
V
min
A
100
Load
3.9
3.7
3.6
3.3
V
min
A
Current Output, Sourcing
V
O
= 0
+190
+160
+140
+100
mA
min
A
Current Output, Sinking
V
O
= 0
190
160
140
100
mA
min
A
Short-Circuit Current Limit
V
O
= 0
250
mA
typ
C
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.04
typ
C
DISABLE (Disabled LOW)
Power-Down Supply Current (+V
S
)
V
DIS
= 0
100
200
240
260
A
max
A
Disable Time
V
IN
= 1V
DC
200
ns
typ
C
Enable Time
V
IN
= 1V
DC
25
ns
typ
C
Off Isolation
G = +2, 5MHz
70
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
, V
IN
= 0
50
mV
typ
C
Turn Off Glitch
G = +2, R
L
= 150
, V
IN
= 0
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (V
DIS
)
V
DIS
= 0
75
130
150
160
A
max
A
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage Range
6.0
6
6
V
max
A
Max Quiescent Current
V
S
=
5V
5.5
5.8
6.0
6.2
mA
max
A
Min Quiescent Current
V
S
=
5V
5.5
5.3
5.1
4.7
mA
min
A
Power-Supply Rejection Ratio (+PSRR)
Input Referred
75
68
66
64
dB
min
A
THERMAL CHARACTERISTICS
Specified Operating Range D, DBV Package
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
DBV
SOT23-6
150
C/W
typ
C
NOTES: (1) Junction Temperature = Ambient for 25
C specifications. (2) Junction Temperature = Ambient at low temperature limit: Junction Temperature = Ambient
+10
C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V
CM
is the input common-mode
voltage. (5) Tested < 3dB below minimum CMRR specification at
CMIR limits.
OPA690
4
SBOS223A
www.ti.com
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
G = +1, V
O
< 0.5Vp-p, R
F
=
25
400
MHz
typ
C
G = +2, V
O
< 0.5Vp-p
190
150
145
140
MHz
typ
C
G = +10, V
O
< 0.5Vp-p
25
18
17
16
MHz
typ
C
Gain-Bandwidth Product
G
10
250
180
170
160
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
20
MHz
typ
C
Peaking at a Gain of +1
V
O
< 0.5Vp-p
5
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 2Vp-p
220
MHz
typ
C
Slew Rate
G = +2, 2V Step
1000
700
670
550
V/
s
typ
C
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
1.6
ns
typ
C
G = +2, V
O
= 2V Step
2.0
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
to V
S
/2
65
60
59
56
dBc
typ
C
R
L
500
to V
S
/2
75
70
68
66
dBc
typ
C
3rd-Harmonic
R
L
= 100
to V
S
/2
68
64
62
60
dBc
typ
C
R
L
500
to V
S
/2
77
73
71
70
dBc
typ
C
Input Voltage Noise
f > 1MHz
5.6
nV/
Hz
typ
C
Input Current Noise
f > 1MHz
3.2
pA/
Hz
typ
C
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150 to V
S
/ 2
0.06
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150 to V
S
/ 2
0.02
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 2.5V, R
L
= 100
to 2.5V
63
56
54
52
dB
min
A
Input Offset Voltage
V
CM
= 2.5V
1.0
4
4.3
4.7
mV
max
A
Average Offset Voltage Drift
V
CM
= 2.5V
10
10
V/
C
max
B
Input Bias Current
V
CM
= 2.5V
+3
8
9
11
A
max
A
Average Bias Current Drift (magnitude)
V
CM
= 2.5V
20
40
nA/
C
max
B
Input Offset Current
V
CM
= 2.5V
0.3
1
1.4
1.6
A
max
A
Average Offset Current Drift
V
CM
= 2.5V
7
9
nA/
C
max
B
INPUT
Least Positive Input Voltage
(5)
1.5
1.6
1.7
1.8
V
max
A
Most Positive Input Voltage
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
= 2.5V
0.5V
63
58
56
54
dB
min
A
Input Impedance
Differential-Mode
V
CM
= 2.5V
92 || 1.4
k
|| pF
typ
C
Common-Mode
V
CM
= 2.5V
2.2 || 1.5
M
|| pF
typ
C
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.6
3.5
V
min
A
R
L
= 100
to 2.5V
3.9
3.7
3.5
3.4
V
min
A
Least Positive Output Voltage
No Load
1
1.2
1.4
1.5
V
min
A
R
L
= 100
to 2.5V
1.1
1.3
1.5
1.7
V
max
A
Current Output, Sourcing
+160
+120
+100
+80
mA
max
A
Current Output, Sinking
160
120
100
80
mA
min
A
Short-Circuit Current
250
mA
typ
C
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.04
typ
C
DISABLE (Disable LOW)
Power-Down Supply Current (+V
S
)
V
DIS
= 0
100
200
240
260
A
max
A
Off Isolation
G = +2, 5MHz
65
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/ 2
50
mV
typ
C
Turn Off Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/ 2
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (V
DIS
)
V
DIS
= 0
75
130
150
160
A
typ
C
POWER SUPPLY
Specified Single-Supply Operating Voltage
5
V
typ
C
Maximum Single-Supply Operating Voltage
12
12
12
V
max
B
Max Quiescent Current
V
S
= +5V
4.9
5.2
5.4
5.6
mA
max
A
Min Quiescent Current
V
S
= +5V
4.9
4.7
4.4
4.0
mA
min
A
Power-Supply Rejection Ratio (+PSRR)
Input Referred
72
dB
typ
C
TEMPERATURE RANGE
Specification: D, DBV
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
DBV
SOT23-6
150
C/W
typ
C
NOTES: (1) Junction Temperature = Ambient for 25
C tested specifications. (2) Junction Temperature = Ambient at low temperature limit: Junction Temperature =
Ambient +10
C at high temperature limit for over temperature tested specifications. (3) Test Levels: (A) 100% tested at 25
C. Over temperature limits by characterization
and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V
CM
is the input
common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at
CMIR limits.
OPA690ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits are tested at +25
C.
R
F
= 402
, R
L
= 100
, and G = +2
,
(see Figure 2 for AC performance only), unless otherwise noted.
OPA690
5
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (3dB/div)
Frequency (MHz)
0.7
10
100
700
6
3
0
3
6
9
12
15
V
O
= 0.5Vp-p
G = +1
R
F
= 25
G = 2
G = 5
G = 10
LARGE-SIGNAL FREQUENCY RESPONSE
10
0.5
1
100
500
Frequency (MHz)
Gain (3dB/div)
9
6
3
0
3
6
V
O
= 4Vp-p
V
O
= 7Vp-p
V
O
= 2Vp-p
V
O
= 1Vp-p
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
400
300
200
100
0
100
200
300
400
G = +2
V
O
= 0.5Vp-p
Output V
oltage (100mV/div)
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output V
oltage (1V/div)
+4
+3
+2
+1
0
1
2
3
4
G = +2
V
O
= 5Vp-p
COMPOSITE VIDEO dG/dP
dG/dP (%/degree)
Number of 150
Loads
1
2
3
4
0.2
0.175
0.15
0.125
0.1
0.075
0.05
0.025
0
dG
dG
dP
dP
No Pull-Down
With 1.3k
Pull-Down
OPA690
402
5V
+5V
75
Video In
402
Optional
1.3k
Pull-Down
DISABLE FEEDTHROUGH vs FREQUENCY
Frequency (Hz)
Feedthrough (5dB/div)
45
50
55
60
65
70
75
80
85
90
95
100
Forward
Reverse
V
DIS
= 0
100k
1M
10M
100M
OPA690
6
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
Load Resistance (
)
100
1000
60
65
70
75
80
85
90
V
O
= 2Vp-p
f = 5MHz
3rd-Harmonic
2nd-Harmonic
5MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
Harmonic Distortion (dBc)
Supply Voltage (
V
S
)
2
2.5
3
3.5
4
4.5
5
5.5
6
60
65
70
75
80
3rd-Harmonic
2nd-Harmonic
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
Frequency (MHz)
0.1
1
10
20
40
50
60
70
80
90
100
V
O
= 2Vp-p
R
L
= 100
2nd-Harmonic
3rd-Harmonic
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
0.1
1
5
60
65
70
75
80
R
L
= 100
f = 5MHz
3rd-Harmonic
2nd-Harmonic
HARMONIC DISTORTION vs NONINVERTING GAIN
Harmonic Distortion (dBc)
Gain (V/V)
1
10
20
40
50
60
70
80
90
3rd-Harmonic
2nd-Harmonic
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
Figure1
HARMONIC DISTORTION vs INVERTING GAIN
Harmonic Distortion (dBc)
Inverting Gain (V/V)
1
10
20
40
50
60
70
80
3rd-Harmonic
2nd-Harmonic
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
R
F
= 1k
OPA690
7
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Current Noise (pA/
Hz)
Voltage Noise (nV/
Hz)
Frequency (Hz)
100
1M
100k
10k
1k
10M
100
10
1
Voltage Noise 5.5nV/
Hz
Current Noise 3.1pA/
Hz
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
3rd-Order Spurious Level (dBc)
Single-Tone Load Power (dBm)
8
6
4
2
0
2
4
6
8
10
30
35
40
45
50
55
60
65
70
75
20MHz
10MHz
50MHz
Load Power at Matched 50
Load,
see Figure 1
RECOMMENDED R
S
vs CAPACITIVE LOAD
R
S
(
)
Capacitive Load (pF)
10
100
1000
80
70
60
50
40
30
20
10
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (50ns/div)
Output V
oltage (0.4V/div)
2.0
1.6
1.2
0.8
0.4
0
V
DIS
(2V/div)
6
4
2
0
G = +2
V
IN
= +1V
V
DIS
Output Voltage
Each Channel
SO-14
Package
Only
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain-to-Capacitive Load (dB)
Frequency (20MHz/div)
0
100
120
140
160
180
20
40
60
80
200
9
6
3
0
3
6
9
402
1k
402
R
S
C
L
V
IN
V
OUT
OPA690
1k
is optional.
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
C
L
= 10pF
G = +2
DISABLE/ENABLE GLITCH
Time (20ns/div)
Output V
oltage (10mV/div)
30
20
10
0
10
20
30
V
DIS
(2V/div)
6
4
2
0
V
i
= 0V
V
DIS
Output Voltage
OPA690
8
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
TYPICAL DC DRIFT OVER TEMPERATURE
Input Offset Voltage (mV)
Input Bias and Offset Currents (
A)
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
2
1.5
1
0.5
0
0.5
1
1.5
2
20
10
0
10
20
Input Offset Current (I
OS
)
Input Offset Voltage (V
OS
)
Input Bias Current (I
B
)
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
Frequency (MHz)
10k
1M
100k
10M
100M
100
90
80
70
60
50
40
30
20
10
0
CMRR
+PSRR
PSRR
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Supply Current (2mA/div)
Output Current (50mA/div)
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
8
7
6
5
4
3
250
200
150
100
50
0
Sourcing Output Current
Sinking Output Current
Quiescent Supply Current
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
V
O
(V)
I
O
(mA)
300
200
100
0
100
200
300
5
4
3
2
1
0
1
2
3
4
5
Output Current Limited
1W Internal
Power Limit
1W Internal
Power Limit
Output Current Limit
100
Load Line
50
Load Line
25
Load Line
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Output Impedance (
)
Frequency (Hz)
10k
1M
100k
10M
100M
10
1
0.1
0.01
OPA690
402
+5V
5V
200
402
Z
O
OPEN-LOOP GAIN AND PHASE
Open-Loop Gain (dB)
Frequency (Hz)
1k
1M
100k
10k
10M
1G
100M
70
60
50
40
30
20
10
0
10
20
Open-Loop Phase (
)
0
30
60
90
120
150
180
210
240
270
Open-Loop Gain
Open-Loop Phase
OPA690
9
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 2 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
Frequency (Hz)
0.7 1
10
700
100
6
3
0
3
6
9
G = +1
R
F
= 25
G = +2
G = +5
G = +10
V
O
= 0.5Vp-p
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (3dB/div)
Frequency (MHz)
0.5
1
10
500
100
9
6
3
0
3
6
V
O
= 2Vp-p
V
O
= 3Vp-p
V
O
= 1Vp-p
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output V
oltage (100mV/div)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
G = +2
V
O
= 0.5Vp-p
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output V
oltage (400mV/div)
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
G = +2
V
O
= 2Vp-p
RECOMMENDED R
S
vs CAPACITIVE LOAD
R
S
(
)
Capacitive Load (pF)
1
10
100
1000
50
45
40
35
30
25
20
15
10
5
0
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain-to-Capacitive Load (dB)
Frequency (20MHz/div)
0
100
120
140
160
180
20
40
60
80
200
9
6
3
0
3
6
9
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
C
L
= 10pF
402
58
714
0.1
F
714
714
402
RS
CL
VIN
+5V
VOUT
+5V
OPA690
OPA690
10
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
, (see Figure 2 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
Resistance (
)
100
1000
60
65
70
75
80
3rd-Harmonic
V
O
= 2Vp-p
f = 5MHz
2nd-Harmonic
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
Frequency (MHz)
0.1
1
10
20
40
50
60
70
80
90
100
V
O
= 2Vp-p
R
L
= 100
to 2.5V
2nd-Harmonic
3rd-Harmonic
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Output Voltage Swing (Vp-p)
0.1
1
3
60
65
70
75
80
3rd-Harmonic
2nd-Harmonic
R
L
= 100
to 2.5V
f = 5MHz
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
3rd-Order Spurious Level (dBc)
Single-Tone Load Power (dBm)
14
12
10
8
6
4
2
0
2
30
35
40
45
50
55
60
65
70
75
20MHz
10MHz
50MHz
Load Power at Matched 50
Load, see Figure 2
OPA690
11
SBOS223A
www.ti.com
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-
tion and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply, Specifica-
tion and Test Circuit.
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA690 provides an exceptional combination of high
output power capability with a wideband, unity-gain stable
voltage feedback op amp using a new high slew rate input
stage. Typical differential input stages used for voltage feed-
back op amps are designed to steer a fixed-bias current to
the compensation capacitor, setting a limit to the achievable
slew rate. The OPA690 uses a new input stage which places
the transconductance element between two input buffers,
using their output currents as the forward signal. As the error
voltage increases across the two inputs, an increasing cur-
rent is delivered to the compensation capacitor. This pro-
vides very high slew rate (1800V/
s) while consuming
relatively low quiescent current (5.5mA). This exceptional
full-power performance comes at the price of a slightly higher
input noise voltage than alternative architectures. The
5.5nV/
Hzinput voltage noise for the OPA690 is exception-
ally low for this type of input stage.
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the
5V
Electrical Characteristics and Typical Characteristics. For test
purposes, the input impedance is set to 50
with a resistor to
ground and the output impedance is set to 50
with a series
output resistor. Voltage swings reported in the specifications
are taken directly at the input and output pins, while output
powers (dBm) are at the matched 50
load. For the circuit of
Figure 1, the total effective load will be 100
|| 804
. The
disable control line is typically left open to ensure normal
amplifier operation. Two optional components are included in
Figure 1. An additional resistor (175
) is included in series
with the noninverting input. Combined with the 25
DC
source resistance looking back towards the signal generator,
this gives an input bias current cancelling resistance that
matches the 200
source resistance seen at the inverting
input (see the DC Accuracy and Offset Control section). In
addition to the usual power-supply decoupling capacitors to
ground, a 0.1
F capacitor is included between the two power-
supply pins. In practical PC board layouts, this optional-added
capacitor will typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration which is the basis of the +5V Specifica-
tions and Typical Characteristics. Though not a "rail-to-rail"
design, the OPA690 requires minimal input and output volt-
age headroom compared to other very wideband voltage
feedback op amps. It will deliver a 3Vp-p output swing on
a single +5V supply with > 150MHz bandwidth. The key
requirement of broadband single-supply operation is to main-
tain input and output signal swings within the useable voltage
ranges at both the input and the output. The circuit of Figure 2
establishes an input midpoint bias using a simple resistive
divider from the +5V supply (two 698
resistors). The input
signal is then AC-coupled into the midpoint voltage bias. The
input voltage can swing to within 1.5V of either supply pin,
giving a 2Vp-p input signal range centered between the
supply pins. The input impedance matching resistor (59
)
used for testing is adjusted to give a 50
input load when the
parallel combination of the biasing divider network is in-
cluded. Again, an additional resistor (50
in this case) is
included directly in series with the noninverting input. This
minimum recommended value provides part of the DC source
resistance matching for the noninverting input bias current. It
is also used to form a simple parasitic pole to roll off the
frequency response at very high frequencies (> 500MHz)
using the input parasitic capacitance to form a bandlimiting
pole. The gain resistor (R
G
) is AC-coupled, giving the circuit
a DC gain of +1, which puts the input DC bias voltage (2.5V)
at the output as well. The output voltage can swing to within
OPA690
+5V
+
DIS
5V
50
Load
50
50
V
O
V
I
50
Source
R
G
402
R
F
402
+
6.8
F
0.1
F
6.8
F
0.1
F
0.1
F
175
OPA690
+5V
+V
S
DIS
V
S
/2
698
100
V
O
V
I
50
59
698
0.1
F
0.1
F
+
6.8
F
0.1
F
R
G
402
R
F
402
50
Source
OPA690
12
SBOS223A
www.ti.com
1V of either supply pin while delivering > 100mA output current.
A demanding 100
load to a midpoint bias is used in this
characterization circuit. The new output stage circuit used in the
OPA690 can deliver large bipolar output currents into this
midpoint load with minimal crossover distortion, as shown in the
+5V supply, 3rd-harmonic distortion plots.
SINGLE-SUPPLY ADC INTERFACE
Most modern, high performance ADC (such as the TI ADS8xx
and ADS9xx series) operate on a single +5V (or lower) power
supply. It has been a considerable challenge for single-supply
op amps to deliver a low distortion input signal at the ADC input
for signal frequencies exceeding 5MHz. The high slew rate,
exceptional output swing, and high linearity of the OPA690
make it an ideal single-supply ADC driver. The circuit on the
front page shows one possible (inverting) interface. Figure 3
shows the test circuit of Figure 2 modified for a capacitive (ADC)
load and with an optional output pull-down resistor (R
B
).
The OPA690 in the circuit of Figure 3 provides > 200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd-harmonic
distortion or 2-tone, 3rd-order intermodulation distortion will be
observed due to the very low crossover distortion in the OPA690
output stage. The limit of output Spurious-Free Dynamic Range
(SFDR) will be set by the 2nd-harmonic distortion. Without R
B
,
the circuit of Figure 3 measured at 10MHz shows an SFDR of
57dBc. This may be improved by pulling additional DC bias
current (I
B
) out of the output stage through the optional R
B
resistor to ground (the output midpoint is at 2.5V for Figure 3).
Adjusting I
B
gives the improvement in SFDR shown in Figure 4.
SFDR improvement is achieved for I
B
values up to 5mA, with
worse performance for higher values.
FIGURE 4. SFDR versus I
B
.
HIGH-PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER
High-frequency DDS Digital-to-Analog Converters (DACs)
require a low distortion output amplifier to retain their
SFDR performance into real-world loads. See Figure 5
for a single-ended output drive implementation. In this
circuit, only one side of the complementary output drive
signal is used. The diagram shows the signal output
current connected into the virtual ground summing junc-
tion of the OPA690, which is set up as a transimpedance
stage or "I-V converter". The unused current output of the
DAC is connected to ground. If the DAC requires its
outputs terminated to a compliance voltage other than
ground for operation, the appropriate voltage level may
be applied to the noninverting input of the OPA690. The
FIGURE 3. Single-Supply ADC Input Driver.
OPA690
402
50
402
59
1Vp-p
698
698
V
I
+5V
DIS
0.1
F
R
S
30
I
B
R
B
50pF
0.1
F
2.5V DC
1V AC
ADC Input
Power-Supply Decoupling Not Shown
70
68
66
64
62
60
58
56
54
52
50
Output Pull-Down Current (mA)
0
1
2
3
4
5
6
7
8
9
10
SFDR (dBc)
V
O
= 2Vp-p, 10MHz
OPA690
13
SBOS223A
www.ti.com
DC gain for this circuit is equal to R
F
. At high frequencies,
the DAC output capacitance will produce a zero in the noise
gain for the OPA690 that may cause peaking in the closed-
loop frequency response. C
F
is added across R
F
to compen-
sate for this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in the feed-
back network should be set to:
1 2
4
/
/
R C
GBP
R C
F
F
F
D
=
which will give a closed-loop transimpedance bandwidth
f
3dB
, of approximately:
f
GBP
R C
dB
F
D
/
3
2
=
HIGH POWER LINE DRIVER
The large output swing capability of the OPA690 and its high
current capability allows it to drive a 50
line with a peak-to-
peak signal up to 4Vp-p at the load, or 8Vp-p at the output
FIGURE 6. High Power Coax Line Driver.
FIGURE 5. DAC Transimpedance Amplifier.
of the amplifier using a single 12V supply. Figure 6 shows
such a circuit set for a gain of 8 to the output or 4 to the load.
The 5pF capacitor in the feedback loop provides added
bandwidth control for the signal path.
SINGLE-SUPPLY ACTIVE FILTERS
The high bandwidth provided by the OPA690, while operat-
ing on a single +5V supply, lends itself well to high-frequency
active filter designs. Again, the key additional requirement is
to establish the DC operating point of the signal near the
supply midpoint for highest dynamic range. Figure 7 shows
an example design of a 5MHz low-pass Butterworth filter
using the Sallen-Key topology.
Both the input signal and the gain setting resistor are AC-
coupled using 0.1
F blocking capacitors (actually giving
bandpass response with the low-frequency pole set to 32kHz
for the component values shown). As discussed for Figure 2,
this allows the midpoint bias formed by the two 1.87k
resistors to appear at both the input and output pins. The
FIGURE 7. Single-Supply, High-Frequency Active Filter.
OPA690
High-Speed
DAC
V
O
= I
O
R
F
R
F
C
F
GBP
Gain Bandwidth
Product (Hz) for the OPA690
C
D
I
O
I
O
50
OPA690
2k
2k
0.1
F
400
50
50
+12V
5pF
1Vp-p
50
Source
8Vp-p
4Vp-p
50
Load
OPA690
1.5k
432
137
500
1.87k
1.87k
V
I
+5V
DIS
0.1
F
150pF
0.1
F
100pF
4V
I
5MHz, 2nd-Order
Butterworth Filter
Gain (dB)
Frequency (Hz)
5MHz, 2nd-Order Butterworth Filter Response
100k
1M
10M
15
10
5
0
5
OPA690
14
SBOS223A
www.ti.com
midband signal gain is set to +4 (12dB) in this case. The
capacitor to ground on the noninverting input is intentionally
set larger to dominate input parasitic terms. At a gain of +4,
the OPA690 on a single supply will show ~80MHz small- and
large-signal bandwidth. The resistor values have been slightly
adjusted to account for this limited bandwidth in the amplifier
stage. Tests of this circuit show a precise 5MHz, 3dB point
with a maximally flat passband (above the 32kHz AC-cou-
pling corner), and a maximum stopband attenuation of 36dB
at the amplifier's 3dB bandwidth of 80MHz.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evalu-
ation of circuit performance using the OPA690 in its three
package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documenta-
tion. The summary information for these boards is shown
below:
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA690ID
SO-8
DEM-OPA68xU
SBOU009
OPA690IDBV
SOT23-6
DEM-OPA6xxN
SBOU010
The board can be requested on Texas Instruments' web site
(www.ti.com.).
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA690 is available through the Texas
Instruments internet web page (http://www.ti.com). These
models do a good job of predicting small-signal AC and
transient performance under a wide variety of operating
conditions. They do not do as well in predicting the harmonic
distortion or dG/dP characteristics. These models do not
attempt to distinguish between the package types in their
small-signal AC performance.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA690 is a unity-gain stable voltage feedback op
amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on these
values are set by dynamic range (noise and distortion) and
parasitic capacitance considerations. For a noninverting unity-
gain follower application, the feedback connection should be
made with a 25
resistor, not a direct short. This will isolate the
inverting input capacitance from the output pin and improve the
frequency response flatness. Usually, for G > 1 application, the
feedback resistor value should be between 200
and 1.5k
.
Below 200
, the feedback network will present additional
output loading which can degrade the harmonic distortion
performance of the OPA690. Above 1.5k
, the typical parasitic
capacitance (approximately 0.2pF) across the feedback resistor
may cause unintentional band-limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of R
F
and R
G
(see Figure 1) to be less than approximately 300
. The
combined impedance R
F
|| R
G
interacts with the inverting input
capacitance, placing an additional pole in the feedback network
and thus, a zero in the forward response. Assuming a 2pF total
parasitic on the inverting node, holding R
F
|| R
G
< 300
will keep
this pole above 250MHz. By itself, this constraint implies that the
feedback resistor R
F
can increase to several k
at high gains.
This is acceptable as long as the pole formed by R
F
and any
parasitic capacitance appearing in parallel is kept out of the
frequency range of interest.
BANDWIDTH VERSUS GAIN: NONINVERTING
OPERATION
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the noninverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90
, as
it does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA690 is
compensated to give a slightly peaked response in a
noninverting gain of 2 (see Figure 1). This results in a typical
gain of +2 bandwidth of 220MHz, far exceeding that pre-
dicted by dividing the 300MHz GBP by 2. Increasing the gain
will cause the phase margin to approach 90
and the band-
width to more closely approach the predicted value of (GBP/
NG). At a gain of +10, the 30MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted using the
simple formula and the typical GBP of 300MHz.
Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2 signal
gain, is to add an 804
resistor across the two inputs in the
circuit of Figure 1. A similar technique may be used to reduce
peaking in unity-gain (voltage follower) applications. For
example, by using a 402
feedback resistor along with a
402
resistor across the two op amp inputs, the voltage
follower response will be similar to the gain of +2 response
of Figure 2. Further reducing the value of the resistor across
the op amp inputs will further dampen the frequency re-
sponse due to increased noise gain.
The OPA690 exhibits minimal bandwidth reduction going to
single-supply (+5V) operation as compared with
5V. This is
because the internal bias control circuitry retains nearly
constant quiescent current as the total supply voltage be-
tween the supply pins is changed.
OPA690
15
SBOS223A
www.ti.com
INVERTING AMPLIFIER OPERATION
Since the OPA690 is a general-purpose, wideband voltage
feedback op amp, all of the familiar op amp application
circuits are available to the designer. Inverting operation is
one of the more common requirements and offers several
performance benefits. Figure 8 shows a typical inverting
configuration where the I/O impedances and signal gain from
Figure 1 are retained in an inverting circuit configuration.
FIGURE 8. Gain of 2 Example Circuit.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 8, the R
M
value
combines in parallel with the external 50
source imped-
ance, yielding an effective driving impedance of 50
|| 67
= 28.6
. This impedance is added in series with R
G
for
calculating the noise gain (NG). The resultant NG is 2.8 for
Figure 8, as opposed to only 2 if R
M
could be eliminated as
discussed above. The bandwidth will therefore be slightly
lower for the gain of 2 circuit of Figure 8 than for the gain
of +2 circuit of Figure 1.
The third important consideration in inverting amplifier design
is setting the bias current cancellation resistor on the
noninverting input (R
B
). If this resistor is set equal to the total
DC resistance looking out of the inverting node, the output
DC error, due to the input bias currents, will be reduced to
(Input Offset Current) R
F
. If the 50
source impedance is
DC-coupled in Figure 8, the total resistance to ground on the
inverting input will be 228
. Combining this in parallel with
the feedback resistor gives the R
B
= 146
used in this
example. To reduce the additional high frequency noise
introduced by this resistor, it is sometimes bypassed with a
capacitor. As long as R
B
< 350
, the capacitor is not required
since the total noise contribution of all other terms will be less
than that of the op amp's input noise voltage. As a minimum,
the OPA690 requires an R
B
value of 50
to damp out
parasitic-induced peaking--a direct short to ground on the
noninverting input runs the risk of a very high frequency
instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
The OPA690 provides output voltage and current capabilities
that are unsurpassed in a low-cost monolithic op amp. Under
no-load conditions at +25
C, the output voltage typically
swings closer than 1V to either supply rail; the tested swing
limit is within 1.2V of either rail. Into a 15
load (the minimum
tested load), it is tested to deliver more than
160mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA690's output drive capabilities,
noting that the graph is bounded by a "Safe Operating Area"
of 1W maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the OPA690 can
drive
2.5V into 25
or
3.5V into 50
without exceeding the
output capabilities or the 1W dissipation limit. A 100
load
line (the standard test circuit load) shows the full
3.9V
output swing capability, as shown in the typical specifica-
tions.
OPA690
50
R
F
402
R
G
200
R
B
146
R
M
67
Source
DIS
+5V
5V
R
O
50
0.1
F
6.8
F
+
0.1
F
0.1
F
6.8
F
+
50
Load
In the inverting configuration, three key design consider-
ations must be noted. The first is that the gain resistor (R
G
)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted-pair, long
PC board trace, or other transmission line conductor), R
G
may be set equal to the required termination value and R
F
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R
G
to 50
for input matching eliminates the need for R
M
but requires a
100
feedback resistor. This has the interesting advantage
that the noise gain becomes equal to 2 for a 50
source
impedance--the same as the noninverting circuits consid-
ered above. However, the amplifier output will now see the
100
feedback resistor in parallel with the external load. In
general, the feedback resistor should be limited to the 200
to 1.5k
range. In this case, it is preferable to increase both
the R
F
and R
G
values, as shown in Figure 8, and then
achieve the input matching impedance with a third resistor
(R
M
) to ground. The total input impedance becomes the
parallel combination of R
G
and R
M
.
OPA690
16
SBOS223A
www.ti.com
The minimum specified output voltage and current specifica-
tions over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown
in the tested tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V
BE
's (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown in
the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum speci-
fied operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA690. The circuit acts to limit the maxi-
mum source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA690 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest and
most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the capaci-
tive load pole, thus increasing the phase margin and improv-
ing stability.
The Typical Characteristics show the recommended R
S
versus capacitive load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA690. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily exceed this value. Always consider this
effect carefully, and add the recommended series resistor as
close as possible to the OPA690 output pin (see Board
Layout Guidelines).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA690 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of R
S
to flatten
the response at the load. Increasing the noise gain will
reduce the peaking as described previously. The circuit of
Figure 9 demonstrates this technique, allowing lower values
of R
S
to be used for a given capacitive load.
OPA690
402
175
402
+5V
50
50
C
L
R
NG
V
O
R
5V
Power-supply decoupling not shown.
FIGURE 9. Capacitive Load Driving with Noise Gain Tuning.
FIGURE 10. Required R
S
vs Noise Gain.
100
90
80
70
60
50
40
30
20
10
0
Capacitive Load (pF)
1
10
100
1000
R
S
(
)
NG = 2
NG = 3
NG = 4
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing the
unloaded phase margin for the op amp. Although this tech-
nique will reduce the required R
S
resistor for a given capacitive
load, it does increase the noise at the output. It also will
decrease the loop gain, slightly decreasing the distortion per-
formance. If, however, the dominant distortion mechanism
arises from a high R
S
value, significant dynamic range im-
provement can be achieved using this technique. Figure 10
shows the required R
S
versus C
LOAD
parametric on noise gain
using this technique. This is the circuit of Figure 9 with R
NG
adjusted to increase the noise gain (increasing the phase
margin) then sweeping C
LOAD
and finding the required R
S
to
get a flat frequency response. This plot also gives the required
R
S
versus C
LOAD
for the OPA690 operated at higher signal
gains.
DISTORTION PERFORMANCE
The OPA690 provides good distortion performance into
a 100
load on
5V supplies. Relative to alternative solu-
tions, it provides exceptional performance into lighter loads
and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power
OPA690
17
SBOS223A
www.ti.com
levels, the 2nd-harmonic will dominate the distortion with a
negligible 3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes
the feedback network; in the noninverting configuration (see
Figure 1) this is sum of R
F
+ R
G
, while in the inverting
configuration, it is just R
F
. Also, providing an additional
supply decoupling capacitor (0.1
F) between the supply pins
(for bipolar operation) improves the 2nd-order distortion
slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The new output stage
used in the OPA690 actually holds the difference between
fundamental power and the 2nd- and 3rd-harmonic powers
relatively constant with increasing output power until very
large output swings are required (> 4Vp-p). This also shows
up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are moder-
ately low at low output power levels. The output stage
continues to hold them low even as the fundamental power
reaches very high levels. As the Typical Characteristics
show, the spurious intermodulation powers do not increase
as predicted by a traditional intercept model. As the funda-
mental power level increases, the dynamic range does not
decrease significantly. For 2 tones centered at 20MHz, with
10dBm/tone into a matched 50
load (i.e., 2Vp-p for each
tone at the load, which requires 8Vp-p for the overall 2-tone
envelope at the output pin), the Typical Characteristics show
47dBc difference between the test tone powers and the 3rd-
order intermodulation spurious powers. This performance
improves further when operating at lower frequencies.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.5nV/
Hz input voltage noise for
the OPA690 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 11 shows the op amp noise analysis model with all the noise
terms included. In this model, all noise terms are taken to be noise
voltage or current density terms in either nV/
Hz or pA/
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 11.
(1)
E
E
I
R
kTR
NG
I R
kTR NG
O
NI
BN S
S
BI F
F
=
+
(
)
+
+
(
)
+
2
2
2
2
4
4
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at the
noninverting input, as shown in Equation 2.
(2)
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN S
S
BI F
F
=
+
(
)
+
+
+
2
2
2
4
4
Evaluating these two equations for the OPA690 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 12.3nV/
Hz and a total equivalent input spot
noise voltage of 6.1nV/
Hz. This is including the noise added
by the bias current cancellation resistor (175
) on the
noninverting input. This total input-referred spot noise volt-
age is only slightly higher than the 5.5nV/
Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
300
. Keeping both (R
F
|| R
G
) and the noninverting input
source impedance less than 300
will satisfy both noise and
frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capacitive
decoupling across the bias current cancellation resistor (R
B
)
for the inverting op amp configuration of Figure 8 is not
required.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA690
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically
8
A at each input terminal),
the close matching between them may be used to reduce the
output DC error caused by this current. The total output offset
voltage may be considerably reduced by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the configura-
tion of Figure 1, using worst-case +25
C input offset voltage
and current specifications, gives a worst-case output offset
voltage equal to: (NG = noninverting signal gain)
(NG V
OS(MAX)
)
(R
F
I
OS(MAX)
)
=
(2 4mV)
(402
1
A)
=
8.4mV
FIGURE 11. Op Amp Noise Analysis Model.
4kT
R
G
R
G
R
F
R
S
OPA690
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
OPA690
18
SBOS223A
www.ti.com
LOW, additional current is pulled through the 15k
resistor,
eventually turning on those two diodes (
75
A). At this point,
any further current pulled out of V
DIS
goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately 0V. This shuts off the collector current out of Q1,
turning the amplifier off. The supply current in the disable
mode are only those required to operate the circuit of Figure
13. Additional circuitry ensures that turn-on time occurs
faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA690 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (R
F
+ R
G
) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (R
F
+ R
G
) and the isolation will be very poor as a result.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 14
shows these glitches for the circuit of Figure 1 with the input
signal at 0V. The glitch waveform at the output pin is plotted
along with the DIS pin voltage.
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be consid-
ered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 12 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.
FIGURE 13. Simplified Disable Control Circuit.
FIGURE 12. DC-Coupled, Inverting Gain of 2, with Offset
Adjustment.
FIGURE 14. Disable/Enable Glitch.
R
F
1k
200mV Output Adjustment
= = 2
Supply Decoupling
Not Shown
5k
5k
328
0.1
F
R
G
500
V
I
20k
10k
0.1
F
5V
+5V
OPA690
+5V
5V
V
O
V
O
V
I
R
F
R
G
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
DISABLE OPERATION
The OPA690 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA690 will operate normally. To
disable, the control pin must be asserted LOW. Figure 13
shows a simplified internal circuit for the disable control
feature.
In normal operation, base current to Q1 is provided through
the 110k
resistor, while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1's emitter. As V
DIS
is pulled
DISABLE/ENABLE GLITCH
Time (20ns/div)
Output V
oltage (10mV/div)
30
20
10
0
10
20
30
V
DIS
(2V/div)
6
4
2
0
V
i
= 0V
V
DIS
Output Voltage
OPA690
19
SBOS223A
www.ti.com
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1
F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1
F) across
the two power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2
F to 6.8
F)
decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA690. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded resis-
tors can also provide good high-frequency performance.
Again, keep their leads and PC board traces as short as
possible. Never use wirewound type resistors in a high-
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 1.5k
,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor val-
ues as low as possible consistent with load driving consider-
ations. The 402
feedback used in the Electrical Character-
istics is a good starting point for design. Note that a 25
feedback resistor, rather than a direct short, is suggested for
the unity-gain follower application. This effectively isolates
the inverting input capacitance from the output pin that would
otherwise cause an additional peaking in the gain of +1
frequency response.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 1k
series resistor between the logic gate
and the DIS input pin will provide adequate bandlimiting
using just the parasitic input capacitance on the DIS pin
while still ensuring adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA690,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P
DL
= V
S
2
/(4 R
L
)
where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA690IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
C and driving a grounded 20
load.
P
D
= 10V 6.2mA + 5
2
/(4 (20
|| 804
)) = 382mW
Maximum T
J
= +85
C + (0.38W 150
C/W) = 142
C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower tested junction temperatures. The highest pos-
sible internal dissipation will occur if the load requires current
to be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The output V-I plot shown in the
Typical Characteristics include a boundary for 1W maximum
internal power dissipation under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA690 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
OPA690
20
SBOS223A
www.ti.com
FIGURE 15. Internal ESD Protection.
External
Pin
+V
CC
V
CC
Internal
Circuitry
d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of Recommended R
S
vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an R
S
since the
OPA690 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an R
S
are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50
environment is normally not necessary
on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA690
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA690 allows multiple destination devices to be
handled as separate transmission lines, each with their own
series and shunt terminations. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set the series
resistor value as shown in the plot of "Recommended R
S
vs
Capacitive Load". This will not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal attenua-
tion due to the voltage divider formed by the series output
into the terminating impedance.
e) Socketing a high-speed part like the OPA690 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA690
onto the board.
INPUT AND ESD PROTECTION
The OPA690 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table. All device pins are protected with internal
ESD protection diodes to the power supplies as shown in
Figure 15.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply
parts driving into the OPA690), current-limiting series resis-
tors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
OPA690
21
SBOS223A
www.ti.com
PACKAGE DRAWINGS
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA690
22
SBOS223A
www.ti.com
PACKAGE DRAWINGS (Cont.)
MPDS026C FEBRUARY 1997 REVISED JANUARY 2001
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0
8
0,25
0,55
0,35
Gage Plane
0,15 NOM
4073253-5/F 10/00
2,60
3,00
0,50
0,25
1,50
1,70
4
6
3
1
2,80
3,00
1,45
0,95
0,05 MIN
Seating Plane
6X
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 are wider than leads 4, 5, 6 for package orientation.
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA690ID
ACTIVE
SOIC
D
8
100
OPA690IDBVR
ACTIVE
SOP
DBV
6
3000
OPA690IDBVT
ACTIVE
SOP
DBV
6
250
OPA690IDR
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
PDF 
ZIP