PCM3000/3001

49%

FPO

PCM3000
PCM3001

PCM3000E

PCM3001E

Stereo Audio CODEC

18-BITS, SERIAL INTERFACE

FEATURES

MONOLITHIC 18-BIT

ADC AND DAC

16- OR 18-BIT INPUT/OUTPUT DATA

STEREO ADC:
Single-ended Voltage Input
64X Oversampling
High Performance:

88dB

THD+N

94dB

SNR

94dB

Dynamic Range

Digital High-Pass Filter

STEREO DAC:
Single-ended Voltage Output
Analog Low Pass Filter
64X Oversampling
High Performance:

90dB

THD+N

98dB

SNR

97dB

Dynamic Range

SPECIAL FEATURES (PCM3000):

Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Analog Loop Back

SAMPLE RATE: Up to 48kHz

SYSTEM CLOCK: 256f

, 384f

, 512f

SINGLE +5V POWER SUPPLY

SMALL PACKAGE: SSOP-28

DESCRIPTION

The PCM3000/3001 is a low cost single chip stereo
audio CODEC (analog-to-digital and digital-to-analog
converter) with single-ended analog voltage input and
output.

Both ADCs and DACs employ delta-sigma modula-
tion with 64X oversampling. The ADCs include a
digital decimation filter and the DACs include an 8X
oversampling digital interpolation filter. The DACs
also include digital attenuation, de-emphasis, infinite
zero detection and soft mute to form a complete
subsystem. The PCM3000/3001 operates with left-
justified, right-justified, I

S or DSP data formats.

PCM3000 can be programmed with a 3-wire serial
interface for special features and data formats.
PCM3001 can be pin-programmed for data formats.

Fabricated on a highly advanced CMOS process, the
PCM3000/3001 is suitable for a wide variety of cost-
sensitive consumer applications where good perfor-
mance is required. Applications include sampling key-
boards, digital mixers, mini-disc recorders, hard-disk
recorders, karaoke systems, DSP-based car stereo,
DAT recorders, and video conferencing.

PDS-1342E

Printed in U.S.A., January, 2000

International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111

Twx: 910-952-1111 · Internet: http://www.burr-brown.com/ · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

For most current data sheet and other product

information, visit www.burr-brown.com

Lch In

Rch In

Analog Front-End

Delta-Sigma

Modulator

Digital

Decimation

Filter

Serial Interface

and

Mode Control

Digital Out

Digital In

Mode Control

System Clock

Lch Out

Rch Out

Low Pass Filter

and

Output Buffer

Multi-Level

Delta-Sigma

Modulator

Digital

Interpolation

Filter

SBAS055

PCM3000/3001

SPECIFICATIONS

All specifications at +25

C, V

= V

= +5V, f

= 44.1kHz, SYSCLK = 384f

, CLKIO Input, 18-bit data, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.

NOTES: (1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB. (2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN,
CLKIO (Schmitt Trigger Input). (3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt Trigger Input, 70k

Internal Pull-Up Resistor). (4) Pin 20:

XTI. (5) Pins 19, 22: DOUT,CLKIO. (6) Pin 21: XTO. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies.
(8) High Pass Filter disabled (PCM3000 only) to measure DC offset. (9) f

= 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used

for performance calculation. (10) With no load on XTO and CLKIO.

PCM3000E/3001E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUT/OUTPUT

Input Logic

Input Logic Level: V

(1)

2.0

VDC

(1)

0.8

VDC

Input Logic Current: I

(2)

Input Logic Current: I

(3)

120

Input Logic Level: V

(4)

0.64 · V

VDC

(4)

0.28 · V

VDC

Input Logic Current: I

(4)

Output Logic

Output Logic Level: V

(5)

OUT

= 1.6mA

4.5

VDC

(5)

OUT

= +3.2mA

0.5

VDC

Output Logic Level: V

(6)

OUT

= 3.2mA

4.5

VDC

(6)

OUT

= +3.2mA

0.5

VDC

CLOCK FREQUENCY

Sampling Frequency (f

)

(7)

44.1

kHz

System Clock Frequency

256f

8.1920

11.2896

12.2880

MHz

384f

12.2880

16.9344

18.4320

MHz

512f

16.3840

22.5792

24.5760

MHz

ADC CHARACTERISTICS

RESOLUTION

Bits

DC ACCURACY

Gain Mismatch Channel-to-Channel

1.0

5.0

% of FSR

Gain Error

2.0

5.0

% of FSR

Gain Drift

ppm of FSR/

Bipolar Zero Error

High-Pass Filter Off

(8)

1.7

%of FSR

Bipolar Zero Drift

High-Pass Filter Off

(8)

ppm of FSR/

DYNAMIC PERFORMANCE

(9)

THD+N: V

= 0.5dB

f = 1kHz

= 60dB

f = 1kHz

Dynamic Range

f = 1kHz, A-Weighted

Signal-to-Noise Ratio

f = 1kHz, A-Weighted

Channel Separation

DIGITAL FILTER PERFORMANCE

Passband

0.454f

Stopband

0.583f

Passband Ripple

0.05

Stopband Attenuation

Delay Time (Latency)

17.4/f

sec

DIGITAL HIGH PASS FILTER RESPONSE

3dB Frequency

0.019f

mHz

ANALOG INPUT

Voltage Range

0dB (Full Scale)

2.9

Vp-p

Center Voltage

2.1

Input Impedance

ANTI-ALIASING FILTER

3dB Frequency

EXT

= 470pF

170

kHz

PCM3000/3001

PCM3000E/3001E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SPECIFICATIONS

(cont.)

All specifications at +25

C, V

= V

= 5V, f

= 44.1kHz, SYSCLK = 384f

, CLKIO Input, 18-bit data, unless otherwise noted.

Supply Voltage

, +V

1, +V

2 ...................................................................... +6.5V

Supply Voltage Differences ...............................................................

0.1V

GND Voltage Differences ..................................................................

0.1V

Digital Input Voltage ...................................................... 0.3 to V

+ 0.3V

Analog Input Voltage ......................................... 0.3 to V

2 + 0.3V

Power Dissipation .......................................................................... 300mW
Input Current ...................................................................................

10mA

Operating Temperature Range ......................................... 25

C to +85

Storage Temperature ...................................................... 55

C to +125

Lead Temperature (soldering, 5s) .................................................. +260

(reflow, 10s) ..................................................... +235

Thermal Resistance,

.............................................................. 100

C/W

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

DAC CHARACTERISTICS

RESOLUTION

Bits

DC ACCURACY
Gain Mismatch Channel-to-Channel

1.0

5.0

% of FSR

Gain Error

1.0

5.0

% of FSR

Gain Drift

ppm of FSR/

Bipolar Zero Error

1.0

% of FSR

Bipolar Zero Drift

ppm of FSR/

DYNAMIC PERFORMANCE

(9)

THD+N: V

OUT

= 0dB (Full Scale)

OUT

= 60dB

Dynamic Range

EIAJ A-Weighted

Signal-to-Noise Ratio (Idle Channel)

EIAJ A-Weighted

Channel Separation

DIGITAL FILTER PERFORMANCE
Passband

0.445f

Stopband

0.555f

Passband Ripple

0.17

Stopband Attenuation

Delay Time

11.1/f

sec

ANALOG OUTPUT
Voltage Range

0.62 · V

Vp-p

Center Voltage

0.5 · V

VDC

Load Impedance

AC Load

ANALOG LOW PASS FILTER
Frequency Response

f = 20kHz

0.16

POWER SUPPLY REQUIREMENTS

Voltage Range: V

4.5

5.5

VDC

4.5

5.5

VDC

Supply Current: +I

, +I

(10)

= V

= 5V

Power Dissipation

= V

= 5V

160

250

TEMPERATURE RANGE

Operation

+85

Storage

+125

PACKAGE

SPECIFIED

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

NUMBER

RANGE

MARKING

NUMBER

(1)

MEDIA

PCM3000E

SSOP-28

324

C to +85

PCM3000E

Rails

PCM3000E/2K

Tape and Reel

PCM3001E

SSOP-28

324

C to +85

PCM3001E

Rails

PCM3001E/2K

Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of "PCM3000E/2K" will get a single 2000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

PCM3000/3001

AGND1

REF

VCOM

OUT

AGND2

RSTB

FMT0

FMT1

FMT2

DGND

CLKIO

XTO

XTI

DOUT

DIN

BCKIN

LRCIN

OUT

AGND1

REF

VCOM

OUT

AGND2

RSTB

DGND

CLKIO

XTO

XTI

DOUT

DIN

BCKIN

LRCIN

OUT

PIN CONFIGURATION--PCM3000

Top View

SSOP

PIN CONFIGURATION--PCM3001

Top View

SSOP

PIN

NAME

I/O

DESCRIPTION

ADC Analog Input, Lch

ADC Analog Power Supply

AGND1

ADC Analog Ground

REF

ADC Input Reference, Lch

REF

ADC Input Reference, Rch

ADC Analog Input, Rch

ADC Anti-alias Filter Capacitor (+), Rch

ADC Anti-alias Filter Capacitor (), Rch

ADC Anti-alias Filter Capacitor (), Lch

ADC Anti-alias Filter Capacitor (+), Lch

VCOM

DAC Output Common

OUT

DAC Analog Output, Rch

AGND2

DAC Analog Ground

DAC Analog Power Supply

OUT

DAC Analog Output, Lch

LRCIN

Sample Rate Clock Input (f

)

(2)

BCKIN

Bit Clock Input

(2)

DIN

Data Input

(2)

DOUT

OUT

Data Output

XTI

Oscillator Input

XTO

OUT

Oscillator Output

CLKIO

I/O

Buffered Output of Oscillator or External Clock
Input

(2)

Digital Power Supply

DGND

Digital Ground

MC/FMT2

Serial Control Bit Clock (PCM3000)/Data
Format Control 2 (PCM3001)

(1, 2)

MD/FMT1

Serial Control Data (PCM3000)/Data Format
Control 1 (PCM3001)

(1, 2)

ML/FMT0

Serial Control Strobe Pulse/Data Format
Control 0 (PCM3001)

(1, 2)

RSTB

Reset

(1, 2)

NOTES: (1) With 70k

typical internal pull-up resistor. (2) Schmitt trigger input.

PIN ASSIGNMENTS PCM3000/3001

PCM3000/3001

TYPICAL PERFORMANCE CURVES
ADC SECTION

At T

= +25

C, V

= V

= +5V, f

= 1.0kHz, f

= 44.1kHz, 18-bit data, V

= 2.9Vp-p, and SYSCLK = 384f

, unless otherwise noted.

THD+N vs TEMPERATURE

Temperature (°C)

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

100

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

60dB

0dB

THD+N vs POWER SUPPLY

(V)

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

4.5

4.75

5.0

5.25

5.5

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

60dB

0dB

THD+N vs SYSTEM CLOCK

and SAMPLING FREQUENCY

System Clock

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

256f

384f

512f

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

44.1kHz

48kHz

60dB

0dB

SNR and DYNAMIC RANGE vs POWER SUPPLY

(V)

SNR (dB)

4.5

4.75

5.0

5.25

5.50

Dynamic Range (dB)

SNR

Dynamic Range

THD+N vs OUTPUT DATA RESOLUTION

Resolution

THD+N at 0dB (%)

THD+N at 60dB (%)

0.01

0.008

0.006

0.004

0.002

16-Bit

18-Bit

4.0

3.0

2.0

1.0

0dB

60dB

PCM3000/3001

TYPICAL PERFORMANCE CURVES
DAC SECTION

At T

= +25

C, V

= V

= +5V, f

= 1.0kHz, f

= 44.1kHz, 18-bit data, and SYSCLK = 384f

, unless otherwise noted.

THD+N vs TEMPERATURE

Temperature (°C)

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

100

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

60dB

0dB

THD+N vs POWER SUPPLY

(V)

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

4.5

4.75

5.0

5.25

5.5

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

60dB

0dB

SNR and DYNAMIC RANGE vs POWER SUPPLY

(V)

SNR (dB)

100

4.5

4.75

5.0

5.25

5.50

Dynamic Range (dB)

100

Dynamic Range

SNR

THD+N vs SYSTEM CLOCK

and SAMPLING FREQUENCY

System Clock

THD+N at 0dB (%)

0.01

0.008

0.006

0.004

0.002

256f

384f

512f

THD+N at 60dB (%)

4.0

3.0

2.0

1.0

44.1kHz

48kHz

60dB

0dB

THD+N vs INPUT DATA RESOLUTION

Resolution

THD+N at 0dB (%)

THD+N at 60dB (%)

0.01

0.008

0.006

0.004

0.002

16-Bit

18-Bit

4.0

3.0

2.0

1.0

0dB

60dB

PCM3000/3001

HIGH PASS FILTER RESPONSE

Normalized Frequency (x f

/1000 Hz)

Amplitude (dB)

0.2

0.0

0.2

0.4

0.6

0.8

1.0

TYPICAL PERFORMANCE CURVES

At T

= +25

C, V

= V

= +5V, and SYSCLK = 384f

, unless otherwise noted.

ADC DIGITAL FILTER

STOPBAND ATTENUATION CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

100

0.25

0.50

0.75

1.00

PASSBAND RIPPLE CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.125

0.250

0.375

0.500

OVERALL CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

100

150

200

ANTI-ALIASING FILTER PASSBAND

FREQUENCY RESPONSE (C

EXT

= 470pF, 1000pF)

Frequency (Hz)

Amplitude (dB)

0.2

0.0

0.2

0.4

0.6

0.8

1.0

100

10k

100k

470pF

1000pF

ANTI-ALIASING FILTER OVERALL

FREQUENCY RESPONSE (C

EXT

= 470pF, 1000pF)

Frequency (Hz)

Amplitude (dB)

100

10k

100k

10M

470pF

1000pF

ANTI-ALIASING FILTER

PCM3000/3001

TYPICAL PERFORMANCE CURVES

At T

= +25

C, V

= V

= +5V, and SYSCLK = 384f

, unless otherwise noted.

DAC DIGITAL FILTER

0 0.4536f

1.3605f

2.2675f

3.1745f

4.0815f

100

OVERALL FREQUENCY CHARACTERISTIC

Frequency (Hz)

PASSBAND RIPPLE CHARACTERISTIC

0.2

0.4

0.6

0.8

0.1134f

0.2268f

0.3402f

0.4535f

Frequency (Hz)

DE-EMPHASIS ERROR (3kHz)

3628

7256

10884

14512

4999.8375

9999.675

14999.5125

19999.35

5442

10884

16326

21768

Frequency (Hz)

0.6
0.4
0.2

0.2
0.4
0.6

0.6
0.4
0.2

0.2
0.4
0.6

0.6
0.4
0.2

0.2
0.4
0.6

DE-EMPHASIS ERROR (44.1kHz)

Frequency (Hz)

DE-EMPHASIS ERROR (48kHz)

Frequency (Hz)

Error (dB)

DE-EMPHASIS FREQUENCY RESPONSE (3kHz)

10k

15k

20k

25k

Frequency (Hz)

2
4
6
8

10
12

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)

10k

15k

20k

25k

Frequency (Hz)

2
4
6
8

10
12

DE-EMPHASIS FREQUENCY RESPONSE (48kHz)

10k

15k

20k

25k

Frequency (Hz)

2
4
6
8

10
12

Level (dB)

1.0

0.5

1.0

Frequency (Hz)

100

10k

24k

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(20Hz~24kHz, Expanded Scale)

ANALOG OUTPUT FILTER

5
0

10
15
20
25
30
35
40
45
50
55

100

10k

100k

10M

Frequency (Hz)

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(10Hz~10MHz)

PCM3000/3001

BLOCK DIAGRAM

FIGURE 1. Analog Front-End (Single-Channel).

15k

470pF

REF

Delta-Sigma

Modulator

(+)

()

REF

2.2µF

4.7µF

Interpolation

Filter

8X Oversampling

Interpolation

Filter

8X Oversampling

Multi-Level

Delta-Sigma

Modulator

Multi-Level

Delta-Sigma

Modulator

Clock/OSC Manager

Reset

RSTB

CLKIO

XTO

AGND2

AGND1

Loop Control

Reference

Mode

Control

Interface

MD (FMT1)

(1)

ML (FMT0)

(1)

MC (FMT2)

(1)

Serial Data

Interface

DOUT

BCKIN

LRCIN

DIN

REF

OUT

VCOM

OUT

Power Supply

XTI

DGND

Analog

Low-Pass

Filter

Analog

Low-Pass

Filter

Decimation

and

High Pass Filter

Delta-Sigma

Modulator

()

(+)

Analog

Front-End

Circuit

Decimation

and

High Pass Filter

Delta-Sigma

Modulator

ADC

DAC

(+)

()

Analog

Front-End

Circuit

NOTE: (1) FMT0, FMT1, FMT2 are for PCM3001 only.

PCM3000/3001

PCM AUDIO INTERFACE

The three-wire digital audio interface for PCM3000/3001 is
on LRCIN (Pin 16), BCKIN (Pin 17), DIN (Pin 18), and
DOUT (Pin 19). The PCM3000/3001 can operate with
seven different data formats. For the PCM3000, these for-
mats are selected through PROGRAM REGISTER 3 in the
software mode. For PCM3001, data formats are selected by

pin-strapping the three format pins. Figures 2, 3 and 4
illustrate audio data input/output format and timing.

PCM3000/3001 can accept 32, 48, or 64 bit clocks (BCKIN)
in one clock of LRCIN. Only formats 0, 2, and 6 can be
selected when 32 bit clocks/LRCIN are applied.

FIGURE 2. Audio Data Input/Output Format.

MSB

Lch

Rch

Lch

Rch

LSB

LRCIN

BCKIN

FORMAT 0: FMT[2:0] = "000"

DIN

MSB

LSB

DAC: 16-Bit, MSB-First, Right-Justified

ADC: 16-Bit, MSB-First, Left-Justified

14 15 16

MSB

LSB

LRCIN

BCKIN

DOUT

MSB

LSB

14 15 16

MSB

Lch

Rch

Lch

Rch

LSB

LRCIN

BCIN

FORMAT 2: FMT[2:0] = "010"

DIN

MSB

LSB

DAC: 16-Bit, MSB-First, Right-Justified

ADC: 16-Bit, MSB-First, Right-Justified

14 15 16

MSB

LSB

LRCIN

BCIN

DOUT

MSB

LSB

14 15 16

MSB

Lch

Rch

Lch

Rch

LSB

LRCIN

BCKIN

FORMAT 1: FMT[2:0] = "001"

DIN

MSB

LSB

DAC: 18-Bit, MSB-First, Right-Justified

ADC: 18-Bit, MSB-First, Left-Justified

16 17 18

MSB

LSB

LRCIN

BCKIN

DOUT

MSB

LSB

16 17 18

PCM3000/3001

FIGURE 3. Audio Data Input/Output Format.

MSB

L-ch

R-ch

L-ch

R-ch

LSB

LRCIN

BCKIN

FORMAT 3: FMT[2:0] = "011"

DIN

MSB

LSB

DAC: 18-Bit, MSB-First, Right-Justified

ADC: 18-Bit, MSB-First, Right-Justified

16 17 18

MSB

LSB

LRCIN

BCKIN

DOUT

MSB

LSB

16 17 18

MSB

L_ch

R-ch

L-ch

R-ch

LSB

LRCIN

BCKIN

FORMAT 5: FMT[2:0] = "101"

DIN

MSB

LSB

DAC: 18-Bit, MSB-First, I

ADC: 18-Bit, MSB-First, I

16 17 18

MSB

LSB

LRCIN

BCKIN

DOUT

MSB

LSB

16 17 18

L-ch

R-ch

L-ch

R-ch

LSB

LRCIN

BCKIN

FORMAT 4: FMT[2:0] = "100 "

DIN

MSB

LSB

DAC: 18-Bit, MSB-First, Left-Justified

ADC: 18-Bit, MSB-First, Left-Justified

16 17 18

MSB

LSB

LRCIN

BCKIN

DOUT

MSB

LSB

16 17 18

L-ch

R-ch

FORMAT 6: FMT[2:0] = "110"

ADC: 16-Bit, MSB-First, DSP-Frame

LRCIN

BCKIN

DOUT

L-ch

R-ch

DAC: 16-Bit, MSB-First, DSP-Frame

MSB

LSB

LRCIN

BCKIN

DIN

MSB

LSB

10 11 12 13 14 15 16

MSB

LSB

MSB

LSB

10 11 12 13 14 15 16

PCM3000/3001

FIGURE 4. Audio Data Input/Output Timing.

256f

, 384f

, or 512f

. When a 384f

or 512f

system clock

is used, the clock is divided into 256f

automatically. The

256f

clock is used to operate the digital filters and the

modulators.

Table I lists the relationship of typical sampling frequencies
and system clock frequencies, and Figures 5 and 6 illustrate
the typical system clock connections and external system
clock timing.

SAMPLING RATE FREQUENCY

SYSTEM CLOCK FREQUENCY

(kHz)

(MHz)

256f

384f

512f

8.1920

12.2880

16.3840

44.1

11.2896

16.9340

22.5792

12.2880

18.4320

24.5760

TABLE I. System Clock Frequencies.

BCH

BCY

BCL

DIH

DIS

LRP

LDO

BDO

BCKIN

LRCIN

DIN

DOUT

1.4V

0.5 x V

BCKIN Pulse Cycle Time

BCY

300ns (min)

BCKIN Pulse Width High

BCH

120ns (min)

BCKIN Pulse Width Low

BCL

120ns (min)

BCKIN Rising Edge to LRCIN Edge

40ns (min)

LRCIN Edge to BCKIN Rising Edge

40ns (min)

LRCIN Pulse Width

LRP

BCY

(min)

DIN Set-up Time

DIS

40ns (min)

DIN Hold Time

DIH

40ns (min)

DOUT Delay Time to BCKIN Falling Edge

BDO

40ns (max)

DOUT Delay Time to LRCIN Edge

LDO

40ns (max)

Rising Time of All Signals

RISE

20ns (max)

Falling Time of All Signals

FALL

20ns (max)

SYSTEM CLOCK

The system clock for the PCM3000/3001 must be either 256f

384f

or 512f

, where f

is the audio sampling frequency. The

system clock can be either a crystal oscillator placed between
XTI (Pin 20) and XTO (Pin 21), or an external clock input. If
an external clock is used, the clock is provided to either XTI
or CLKIO (Pin 22), and XTO is open. The PCM3000/3001
has an XTI clock detection circuit which senses if an XTI
clock is operating. When the external clock is delivered to
XTI, CLKIO is a buffered output of XTI. When XTI is
connected to ground, the external clock must be tied to
CLKIO. For best performance, the "External Clock Input 2"
circuit in Figure 5 is recommended.

The PCM3000/3001 also has a system clock detection circuit
which automatically senses if the system clock is operating at

PCM3000/3001

FIGURE 5. System Clock Connections.

CLKIH

System Clock Pulse Width High

CLKIH

12ns (min)

System Clock Pulse Width Low

CLKIL

12ns (min)

CLKIL

3.2V

XTI or CLKIO

1.4V

2.0V

XTI

CLKIO

0.8V

FIGURE 6. External System Clock Timing.

= C

= 10 to 33pF

256f

Internal System Clock

Clock Divider

256f

Internal System Clock

Clock Divider

XTI

X'tal

XTO

PCM3000/3001

CLKIO

CRYSTAL RESONATOR CONNECTION (X'tal must be fundamental made, parallel resonant)

External Clock

(CMOS I/F)

External Clock

(TTL I/F)

XTI

XTO

PCM3000/3001

EXTERNAL CLOCK INPUT 1: (XTO is open)

CLKIO

256f

Internal System Clock

Clock Divider

XTI

XTO

PCM3000/3001

EXTERNAL CLOCK INPUT 2: (XTO is open)

CLKIO

PCM3000/3001

POWER-ON RESET

Both the PCM3000 and PCM3001 have internal power-on
reset circuitry. Power-on reset occurs when system clock
(XTI or CLKIO) is active and V

> 4.0V. For the PCM3001,

the system clock must complete a minimum of 3 complete
cycles prior to V

> 4.0V to ensure proper reset operation.

The initialization sequence requires 1024 system cycles for
completion, as shown in Figure 7. Figure 10 shows the state
of the DAC and ADC outputs during and after the reset
sequence.

EXTERNAL RESET

The PCM3000 and PCM3001 include a reset input, RSTB
(pin 28). As shown in Figure 8, the external reset signal must
drive RSTB low for a minimum of 40 nanoseconds while
system clock is active in order to initiate the reset sequence.
Initialization starts on the rising edge of RSTB, and requires
1024 system clock cycles for completion. Figure 10 shows
the state of the DAC and ADC outputs during and after the
reset sequence.

FIGURE 9. Control Data Input Format.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

FIGURE 7. Internal Power-On Reset Timing.

1024 System Clock Periods

Reset

Reset Removal

4.4V
4.0V
3.6V

Internal Reset

System Clock

(XTI or CLKIO)

FIGURE 8. External Forced Reset Timing.

1024 System Clock Periods

Reset

Reset Removal

System Clock

(XTI or CLKIO)

Internal Reset

RSTB

RST

= 40ns minimum

PCM3000/3001

SYNCHRONIZATION WITH THE DIGITAL
AUDIO SYSTEM

PCM3000/3001 operates with LRCIN synchronized to the
system clock. The CODEC does not require any specific
phase relationship between LRCIN and the system clock, but
there must be synchronization. If the synchronization be-
tween the system clock and LRCIN changes more than 6 bit
clocks (BCKIN) during one sample (LRCIN) period because
of phase jitter on LRCIN, internal operation of the DAC will
stop within 1/f

, and the analog output will be forced to

bipolar zero (V

/2) until the system clock is re-synchronized

to LRCIN. Internal operation of the ADC will also stop with
1/f

, and the digital output codes will be set to bipolar zero

until re-synchronization occurs. If LRCIN is synchronized
with 5 or less bit clocks to the system clock, operation will be
normal.

Figure 11 illustrates the effects on the output when synchro-
nization is lost. Before the outputs are forced to bipolar zero
(<1/f

seconds), the outputs are not defined and some noise

may occur. During the transitions between normal data and
undefined states, the output has discontinuities, which will
cause output noise.

FIGURE 11. DAC Output and ADC Output When Synchronization is Lost.

FIGURE 10. DAC Output and ADC Output for Reset and Power-Down.

Normal Normal

Synchronous

Asynchronous

within

1/f

Synchronous

Normal

(1)

ZERO

32/f

Undefined Data

Undefined

Data

VCOM

(= 1/2 x V

22.2/f

State of

Synchronization

DAC V

OUT

ADC DOUT

NOTE: (1) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears initally.

Reset

Internal Reset

DAC V

OUT

ADC DOUT

Zero

VCOM

(= 1/2 x V

32/f

4096/f

Reset Removal or Power-Down

(1)

OFF

(2)

NOTES: (1) Power-Down is for PCM3000 only. (2) The HPF transient response
(exponentially attenuationed signal with 200ms time constant) appears intially.

PCM3000/3001

OPERATIONAL CONTROL

PCM3000 can be controlled in a software mode with a three-
wire serial interface on MC (Pin 25), MD (Pin 26), and ML

B15

B14

B13

B12

B11

B10

res

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

res

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

res

PDWN

BYPS

res

ATC

IZD

OUT

DM1

DM0

MUT

res

LOP

FMT2

FMT1

FMT0

LRP

res

MAPPING OF PROGRAM REGISTERS

FIGURE 12. Control Data Input Timing.

MC Pulse Cycle Time

MCY

100ns (min)

MC Pulse Width LOW

MCL

40ns (min)

MC Pulse Width HIGH

MCH

40ns (min)

MD Setup Time

MDS

40ns (min)

MD Hold Time

MDH

40ns (min)

ML Low Level Time

MLL

40ns + 1SYSCLK (min)

ML High Level Time

MLH

40ns + 1SYSCLK (min)

ML Setup Time

MLS

40ns (min)

ML Hold Time

MLH

40ns (min)

SYSCLK: 1/256f

or 1/384f

or 1/512f

1.4V

MLL

MHH

MCH

MCL

MDS

MCY

MLS

MLH

MDH

LSB

FUNCTION

ADC/DAC

DEFAULT (PCM3000)

Audio Data Format (7 Selectable Formats)

ADC/DAC

DAC: 16-bit, MSB-first, Right-Justified

ADC: 16-bit, MSB-first, Left-Justified

LRCIN Polarity

ADC/DAC

Left/Right = High/Low

Loop Back Control

ADC/DAC

OFF

Left Channel Attenuation

DAC

0dB

Right Channel Attenuation

DAC

0dB

Attenuation Control

DAC

Left Channel and Right Channel = Individual Control

Infinite Zero Detection

DAC

OFF

DAC Output Control

DAC

Output Enabled

Soft Mute Control

DAC

OFF

De-emphasis (OFF, 32kHz, 44.1kHz, 48kHz)

DAC

OFF

Power Down Control

ADC

OFF

High Pass Filter Operation

ADC

TABLE II. Selectable Functions.

(Pin 27). Table II indicates selectable functions, and Figures
9 and 12 illustrate control data input format and timing. The
PCM3001 only allows for control of data format.

PCM3000/3001

REGISTER

BIT

NAME

DESCRIPTION

A (1:0)

res

Reserved, should be set to "0"

LDL

DAC Attenuation Data Load Control for Lch

AL (7:0)

Attenuation Data for Lch

A (1:0)

res

Reserved, should be set to "0"

LDR

DAC Attenuation Data Load Control for Rch

AR (7:0)

DAC Attenuation for Rch

A (1:0)

res

Reserved, should be set to "0"

PDWN

ADC Power Down Control

BYPS

ADC High-Pass Filter Operation Control

ATC

DAC Attenuation Data Mode Control

IZD

DAC Infinite Zero Detection Circuit Control

OUT

DAC Output Enable Control

DEM (1:0)

DAC De-emphasis Control

MUT

Lch and Rch Soft Mute Control

A (1:0)

res

Reserved, should be set to "0"

LOP

ADC/DAC Analog Loop-back Control

FMT (2:0)

ADC/DAC Audio Data Format Selection

LRP

ADC/DAC Polarity of LR-clock Selection

TABLE III. Functions of the Registers.

PROGRAM REGISTER (PCM3000)

The software mode allows the user to control special functions.
PCM3000's special functions are controlled using four pro-
gram registers which are 16 bits long. There are four distinct
registers, with bits 9 and 10 determining which register is in
use. Table III describes the functions of the four registers.

PROGRAM REGISTER 0

A (1:0):

Bit 10, 9

These bits define the address for REGISTER 0:

res:

Bit 11 : 15

Reserved

These bits are reserved and should be set to "0".

LDL:

Bit 8

DAC Attenuation Data Load Control for
Left Channel

This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AL (7:0) attenuation data
when this bit is set to "1". When set to "0", the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDR bit in REGISTER 1
has the equivalent function as LDL. When either
LDL or LDR is set to "1", the output level of the
left and right channels are simultaneously con-
trolled.

AL (7:0): Bit 7 :0

DAC Attenuation Data for Left Channel

AL7 and AL0 are MSB and LSB, respectively.
The attenuation level (ATT) is given by:

ATT = 20

log

(ATT data/256) (dB)

AL (7:0)

ATTENUATION LEVEL

00h

dB (Mute)

01h

48.16dB

FEh

0.07dB

FFh

0dB (default)

PROGRAM REGISTER 1

A (1:0):

These bits define the address for REGISTER 1:

res:

Bit 15 : 11

Reserved

These bits are reserved and should be set to "0"

LDR:

Bit 8

DAC Attenuation Data Load Control for
Right Channel

This bit is used to simultaneously set analog
outputs of the left and right channels. The output
level is controlled by AR (7:0) attenuation data
when this bit is set to "1". When set to "0", the
new attenuation data will be stored into a register,
and the output level will remain at the previous
attenuation level. The LDL bit in REGISTER 0
has the equivalent function as LDR. When either
LDL or LDR is set to "1", the output level of the
left and right channels are simultaneously con-
trolled.

AR (7:0): Bit 7 : 0

DAC Attenuation Data for Right
Channel

AR7 and AR0 are MSB and LSB respectively.
See REGISTER 0 for the attenuation formula.

PROGRAM REGISTER 2

A (1:0):

Bit 10, 9

These bits define the address for REGISTER 2:

res:

Bit 15:11, 6 Reserved

These bits are reserved and should be set to "0".

PDWN:

Bit 8

ADC Power-Down Control

This bit places the ADC section in a power-down
mode, forcing the output data to all zeroes. This
has no effect on the DAC section.

PDWN

Power Down Mode Disabled (default)

Power Down Mode Enabled

PCM3000/3001

PROGRAM REGISTER 3

A (1:0):

Bit 10, 9

These bits define the address for REGISTER 3:

res:

Bit 15:11, 8:6, 0

Reserved

These bits are reserved, and should be set to "0".

FMT (2:0) Bit 4:2

Audio Data Format Select

These bits determine the input and output audio
data formats. (default: FMT [2:0] = 000

)

FMT2 FMT1 FMT0

DAC

ADC

Data Format

16-bit, MSB-first,

Right-justified

Left-justified

18-bit, MSB-first,

Right-justified

Left-justified

16-bit, MSB-first,

Right-justified

18-bit, MSB-first,

Right-justified

16-/18-bit, MSB-first,

18-bit, MSB-first,

Left-justified

16-/18-bit, MSB-first, I

18-bit, MSB-first, I

16-bit, MSB-first,

DSP-frame

Reserved

LOP:

Bit 5

ADC to DAC Loop-back Control

When this bit is set to "1", the ADC's audio data
is sent directly to the DAC. The data format will
default to I

S. In Format 6 (DSP Frame), Loop-

back is not supported.

LOP

Loop-back Disable (default)

Loop-back Enable

LRP:

Bit 1

Polarity of LRCIN Applies only to
Formats 0 through 4.

LRP

Left-Channel is "H", Right-Channel is "L". (default)

Left-Channel is "L", Right-Channel is "H".

PCM3001 DATA FORMAT CONTROL

The input and output data formats are controlled by pins 27
(FMT0), 26 (FMT1), and 25 (FMT2). Set these pins to the
same values shown for the bit-mapped PCM3000 controls in
PROGRAM REGISTER 3.

BYPS:

Bit 7

ADC High-Pass Filter Bypass Control

This bit determines enables or disables the high-
pass filter for the ADC.

BYPS

High-Pass Filter Enabled (default)

High-Pass Filter Disabled (bypassed)

ATC:

Bit 5

DAC Attenuation Channel Control

When set to "1", the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ig-
nored.

ATC

Individual Channel Attenuation Data Control (default)

Common Channel Attenuation Data Control

IZD:

Bit 4

DAC Infinite Zero Detection Circuit
Control

This bit enables the Infinite Zero Detection Circuit
in PCM3000. When enabled, this circuit will dis-
connect the analog output amplifier from the delta-
sigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.

IZD

Infinite Zero Detection Disabled (default)

Infinite Zero Detection Enabled

OUT:

Bit 3

DAC Output Enable Control

When set to "1", the outputs are forced to V

(bipolar zero). In this case, all registers in
PCM3000 hold the present data. Therefore, when
set to "0", the outputs return to the previous
programmed state.

OUT

DAC Outputs Enabled (default normal operation)

DAC Outputs Disabled (forced to BPZ)

DM (1:0):Bit 2,1

DAC De-emphasis Control

These bits select the de-emphasis mode as shown
below:

DM1

DM0

De-emphasis OFF (default)

De-emphasis 48kHz ON

De-emphasis 44.1kHz ON

De-emphasis 32kHz ON

MUT:

Bit 0

DAC Soft Mute Control

When set to "1", both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.

MUT

Mute Disable (default)

Mute Enable

PCM3000/3001

FIGURE 13. Typical Connection Diagram for PCM3000/3001.

470pF

4.7µF

2.2µF

(2)

2.2µF

(2)

10 to 33pF

10µF

Interface

Reference

Bias

Analog

Front-End

Decimation

Filter

Interpolation

Filter

LPF and

Buffer

LPF and

Buffer

Digital

Audio

Interface

Analog

Front-End

CLK/OSC

Manager

Delta-Sigma

Post

Low-Pass

Filter

Post

Low-Pass

Filter

(1)

Serial

Control

Format
Control

Digital

Audio

Data

Reset

Line In Left-Channel

+5V

Line In Right-Channel

Line Out Right-Channel

Line Out Left-Channel

NOTES: (1) Bypass capacitor = 0.1µF to 10µF. (2) The input capacitor
affects the pole of the HPF. Example: 2.2µF sets the cut-off frequency
to 4.8Hz, with a 66ms time constant.

APPLICATION AND LAYOUT
CONSIDERATIONS

POWER SUPPLY BYPASSING

The digital and analog power supply lines to PCM3000/
3001 should be bypassed to the corresponding ground pins
with both 0.1

F ceramic and 10

F tantalum capacitors as

close to the device pins as possible. Although PCM3000/
3001 has three power supply lines to optimize dynamic
performance, the use of one common power supply is
generally recommended to avoid unexpected latch-up or pop
noise due to power supply sequencing problems. If separate
power supplies are used, back-to-back diodes are recom-
mended to avoid latch-up problems.

GROUNDING

In order to optimize dynamic performance of PCM3000/
3001, the analog and digital grounds are not internally
connected. PCM3000/3001 performance is optimized with a
single ground plane for all returns. It is recommended to tie
all PCM3000/3001 ground pins with low impedance con-
nections to the analog ground plane. PCM3000/3001 should
reside entirely over this plane to avoid coupling high fre-
quency digital switching noise into the analog ground plane.

VOLTAGE INPUT PINS

A tantalum or aluminum electrolytic capacitor, between 2.2

and 10

F, is recommended as an AC-coupling capacitor at

the inputs. Combined with the 15k

characteristic input

impedance, a 2.2

F coupling capacitor will establish a 4.8Hz

cutoff frequency for blocking DC. The input voltage range
can be increased by adding a series resistor on the analog
input line. This series resistor, when combined with the 15k

input impedance, creates a voltage divider and enables larger
input ranges.

REF

INPUTS

A 4.7

F to 10

F tantalum capacitor is recommended be-

tween V

REF

L, V

REF

R, and AGND to ensure low source

impedance for the ADC's references. These capacitors should
be located as close as possible to the reference pins to reduce
dynamic errors on the ADC reference.

P AND C

N INPUTS

A 470pF to 1000pF film or NPO ceramic capacitor is recom-
mended between C

PL and C

NL, C

PR, and C

NR to

create an anti-alias filter, which will have an 170kHz to
80kHz cut-off frequency. These capacitors should be located
as close as possible to the C

P and C

N pins to avoid

introducing undesirable noise or dynamic errors into the
delta-sigma modulator.

PCM3000/3001

VCOM INPUTS

A 4.7

F to 10

F tantalum capacitor is recommended be-

tween VCOM and AGND to ensure low source impedance
of the DAC output common. This capacitor should be
located as close as possible to the VCOM pin to reduce
dynamic errors on the DAC common.

SYSTEM CLOCK

The quality of the system clock can influence dynamic
performance of both the ADC and DAC in the PCM3000/
3001. The duty cycle, jitter, and threshold voltage at the
system clock input pin must be carefully managed. When
power is supplied to the part, the system clock, bit clock
(BCKIN) and a word clock (LCRIN) should also be supplied
simultaneously. Failure to supply the audio clocks will result
in a power dissipation increase of up to three times normal
dissipation and may degrade long term reliability if the
maximum power dissipation limit is exceeded.

THEORY OF OPERATION

ADC SECTION

The PCM3000/3001 ADC consists of a bandgap reference,
a stereo single-to-differential converter, a fully differential
5th-order delta-sigma modulator, a decimation filter (includ-
ing digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differential
converter, and Figure 14 illustrates the architecture of the
5th-order delta-sigma modulator and transfer functions.

An internal high precision reference with two external ca-
pacitors provides all reference voltages which are required
by the ADC, which defines the full scale range for the
converter. The internal single-to-differential voltage con-
verter saves the space and extra parts needed for external
circuitry required by many delta-sigma converters. The
internal full differential signal processing architecture pro-
vides a wide dynamic range and excellent power supply
rejection performance.

The input signal is sampled at 64X oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a one-bit DAC. The delta-sigma
modulator shapes the quantization noise, shifting it out of
the audio band in the frequency domain. The high order of
the modulator enables it to randomize the modulator out-
puts, reducing idle tone levels.

The 64f

one-bit data stream from the modulator is con-

verted to 1f

18-bit data words by the decimation filter,

which also acts as a low pass filter to remove the shaped
quantization noise. The DC components are removed by a
high pass filter function contained within the decimation
filter.

THEORY OF OPERATION

DAC SECTION

The delta-sigma DAC section of PCM3000/3001 is based on
a 5-level amplitude quantizer and a 3rd-order noise shaper.
This section converts the oversampled input data to 5-level
delta-sigma format. A block diagram of the 5-level delta-
sigma modulator is shown in Figure 15. This 5-level delta-
sigma modulator has the advantage of improved stability
and reduced clock jitter sensitivity over the typical one-bit
(2 level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 64f

for a

256f

system clock. The theoretical quantization noise per-

formance of the 5-level delta-sigma modulator is shown in
Figure 16.

PCM3000/3001

FIGURE 16. Quantization Noise Spectrum.

Out

64f

(256f

)

18-Bit

5-level Quantizer

FIGURE 15. 5-Level

Modulator Block Diagram.

3rd ORDER

MODULATOR

Frequency (kHz)

Gain (dB)

10
20
30
40
50
60
70
80
90

100
110
120
130
140
150

5th SW-CAP

Integrator

4th SW-CAP

Integrator

3rd SW-CAP

Integrator

2nd SW-CAP

Integrator

1st SW-CAP

Integrator

1-Bit
DAC

H(z)

Qn(z)

Analog In

X(z)

Digital Out

Y(z)

Y(z) = STF(z) · X(z) + NTF(z) · Qn(z)
Signal Transfer Function
Noise Transfer Function

STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1/ [1 + H(z)]

Comparator

FIGURE 14. Simplified 5th-Order Delta-Sigma Modulator.

PACKAGING INFORMATION

ORDERABLE DEVICE

STATUS(1)

PACKAGE TYPE

PACKAGE DRAWING

PINS

PACKAGE QTY

PCM3000E

ACTIVE

SSOP

PCM3000E/2K

ACTIVE

SSOP

2000

PCM3001E

ACTIVE

SSOP

PCM3001E/2K

ACTIVE

SSOP

2000

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2003

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2003, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PCM3001E/2K

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