SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B MARCH 1987 REVISED MAY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These devices contain four independent 2-input
OR gates. They perform the Boolean functions
Y = A + B or Y = A
B in positive logic.
The SN54F32 is characterized for operation over
the full military temperature range of 55
C to
125
C. The SN74F32 is characterized for
operation from 0
C to 70
C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
Y
H
X
H
X
H
H
L
L
L
logic symbol
1
1A
2
1B
4
2A
5
2B
9
3A
10
3B
12
4A
13
4B
1Y
3
2Y
6
3Y
8
4Y
11
1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each gate (positive logic)
A
B
Y
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54F32 . . . J PACKAGE
SN74F32 . . . D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
SN54F32 . . . FK PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
CC
NC No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B MARCH 1987 REVISED MAY 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
1.2 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range
30 mA to 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54F32
SN74F32
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High-level output current
1
1
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54F32
SN74F32
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V,
IOH = 1 mA
2.5
3.4
2.5
3.4
V
VOH
VCC = 4.75 V,
IOH = 1 mA
2.7
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.3
0.5
0.3
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.5 V
0.6
0.6
mA
IOS
VCC = 5.5 V,
VO = 0
60
150
60
150
mA
ICCH
VCC = 5.5 V
6.1
9.2
6.1
9.2
mA
ICCL
VCC = 5.5 V,
VI = 0
10.3
15.5
10.3
15.5
mA
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
ICCH is measured with one input per gate at 4.5 V and all others grounded.
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B MARCH 1987 REVISED MAY 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25
C
SN54F32
SN74F32
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tPLH
A or B
Y
2.2
3.8
5.6
2.2
7.5
2.2
6.6
ns
tPHL
A or B
Y
2.2
3.6
5.3
1.7
7.5
2.2
6.3
ns
SN54F32, SN74F32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SDFS044B MARCH 1987 REVISED MAY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL
+ 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
Open
7 V
Open
7 V
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
7 V
500
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
0.3 V
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright
1999, Texas Instruments Incorporated
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