SN54LV132A, SN74LV132A
QUADRUPLE POSITIVE NAND GATES
WITH SCHMITT TRIGGER INPUTS
SCLS394H - APRIL 1998 - REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 5.5-V V
CC
Operation
D
Max t
pd
of 9 ns at 5 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25
C
D
Support Mixed-Mode Voltage Operation on
All Ports
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
description/ordering information
The 'LV132A devices are quadruple
positive-NAND gates designed for 2-V to 5.5-V
V
CC
operation.
The 'LV132A devices perform the Boolean
function Y = A
B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but
because of the Schmitt action, it has different input
threshold levels for positive- and negative-going
signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC - D
Tube of 25
SN74LV132AD
LV132A
SOIC - D
Reel of 2500
SN74LV132ADR
LV132A
SOP - NS
Reel of 2000
SN74LV132ANSR
74LV132A
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74LV132ADBR
LV132A
-40
C to 85
C
Tube of 90
SN74LV132APW
TSSOP - PW
Reel of 2000
SN74LV132APWR
LV132A
TSSOP - PW
Reel of 250
SN74LV132APWT
LV132A
TVSOP - DGV
Reel of 2000
SN74LV132ADGVR
LV132A
CDIP - J
Tube of 25
SNJ54LV132AJ
SNJ54LV132AJ
-55
C to 125
C
CFP - W
Tube of 150
SNJ54LV132AW
SNJ54LV132AW
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54LV132AFK
SNJ54LV132AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV132A . . . J OR W PACKAGE
SN74LV132A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54LV132A . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
SN54LV132A, SN74LV132A
QUADRUPLE POSITIVE NAND GATES
WITH SCHMITT TRIGGER INPUTS
SCLS394H - APRIL 1998 - REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54LV132A, SN74LV132A
QUADRUPLE POSITIVE NAND GATES
WITH SCHMITT TRIGGER INPUTS
SCLS394H - APRIL 1998 - REVISED APRIL 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LV132A
SN74LV132A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
-50
-50
A
IOH
High-level output current
VCC = 2.3 V to 2.7 V
-2
-2
IOH
High-level output current
VCC = 3 V to 3.6 V
-6
-6
mA
VCC = 4.5 V to 5.5 V
-12
-12
mA
VCC = 2 V
50
50
A
IOL
Low-level output current
VCC = 2.3 V to 2.7 V
2
2
IOL
Low-level output current
VCC = 3 V to 3.6 V
6
6
mA
VCC = 4.5 V to 5.5 V
12
12
mA
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV132A
SN74LV132A
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VT+
2.5 V
1.75
1.75
VT+
Positive-going
input threshold voltage
3.3 V
2.31
2.31
V
Positive-going
input threshold voltage
5 V
3.5
3.5
V
VT-
2.5 V
0.75
0.75
VT-
Negative-going
input threshold voltage
3.3 V
0.99
0.99
V
Negative-going
input threshold voltage
5 V
1.5
1.5
V
VT
2.5 V
0.25
1
0.25
1
VT
Hysteresis (VT+ - VT-)
3.3 V
0.33
1.32
0.33
1.32
V
Hysteresis (VT+ - VT-)
5 V
0.5
2
0.5
2
V
IOH = -50
A
2 V to 5.5 V
VCC - 0.1
VCC - 0.1
VOH
IOH = -2 mA
2.3 V
2
2
V
VOH
IOH = -6 mA
3 V
2.48
2.48
V
IOH = -12 mA
4.5 V
3.8
3.8
IOL = 50
A
2 V to 5.5 V
0.1
0.1
VOL
IOL = 2 mA
2.3 V
0.4
0.4
V
VOL
IOL = 6 mA
3 V
0.44
0.44
V
IOL = 12 mA
4.5 V
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
1
1
A
ICC
VI = VCC or GND, IO = 0
5.5 V
20
20
A
Ioff
VI or VO = 0 to 5.5 V
0
5
5
A
Ci
VI = VCC or GND
3.3 V
1.9
1.9
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV132A, SN74LV132A
QUADRUPLE POSITIVE NAND GATES
WITH SCHMITT TRIGGER INPUTS
SCLS394H - APRIL 1998 - REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV132A
SN74LV132A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
Y
CL = 15 pF
7.9*
16.5*
1*
18.5*
1
18.5
ns
tpd
A or B
Y
CL = 50 pF
10.8
20.2
1
23
1
23
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV132A
SN74LV132A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
Y
CL = 15 pF
5.6*
11.9*
1*
14*
1
14
ns
tpd
A or B
Y
CL = 50 pF
7.6
15.4
1
17.5
1
17.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54LV132A
SN74LV132A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A or B
Y
CL = 15 pF
3.9*
7.7*
1*
9*
1
9
ns
tpd
A or B
Y
CL = 50 pF
5.3
9.7
1
11
1
11
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25
C (see Note 5
)
PARAMETER
SN74LV132A
UNIT
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.21
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
-0.09
-0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.12
V
VIH(D)
High-level dynamic input voltage
2.31
V
VIL(D)
Low-level dynamic input voltage
0.99
V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
3.3 V
7.5
pF
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
5 V
11.2
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV132A, SN74LV132A
QUADRUPLE POSITIVE NAND GATES
WITH SCHMITT TRIGGER INPUTS
SCLS394H - APRIL 1998 - REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC
VOH -
0.3 V
Figure 1. Load Circuit and Voltage Waveforms
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