SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D JULY 1985 REVISED APRIL 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Bidirectional Transceivers
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
Driver Output Capability . . .
60 mA Max
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Receiver Input Impedance . . . 12 k
Min
D
Receiver Input Sensitivity . . .
200 mV
D
Receiver Input Hysteresis . . . 50 mV Typ
D
Operate From Single 5-V Supply
description/ordering information
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional
data communication on multipoint bus transmission lines. They are designed for balanced transmission lines
and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V
CC
= 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (P)
Tube of 50
SN75176BP
SN75176BP
0
C to 70
C
SOIC (D)
Tube of 75
SN75176BD
75176B
0
C to 70
C
SOIC (D)
Reel of 2500
SN75176BDR
75176B
SOP (PS)
Reel of 2000
SN75176BPSR
A176B
PDIP (P)
Tube of 50
SN65176BP
SN65176BP
40
C to 105
C
SOIC (D)
Tube of 75
SN65176BD
65176B
SOIC (D)
Reel of 2500
SN65176BDR
65176B
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
SN65176B . . . D OR P PACKAGE
SN75176B . . . D, P, OR PS PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D JULY 1985 REVISED APRIL 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150
C. The receiver features a minimum input impedance of 12 k
,
an input sensitivity of
200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
Function Tables
DRIVER
INPUT
ENABLE
OUTPUTS
D
DE
A
B
H
H
H
L
L
H
L
H
X
L
Z
Z
RECEIVER
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
AB
RE
R
VID
0.2 V
L
H
0.2 V < VID < 0.2 V
L
?
VID
0.2 V
L
L
X
H
Z
Open
L
?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic diagram (positive logic)
DE
RE
R
6
7
3
1
2
B
A
Bus
D
4
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D JULY 1985 REVISED APRIL 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics of inputs and outputs
Output
85
NOM
TYPICAL OF RECEIVER OUTPUT
Input/Output
Port
960
NOM
16.8 k
NOM
TYPICAL OF A AND B I/O PORTS
Driver input: R(eq) = 3 k
NOM
Enable inputs: R(eq )= 8 k
NOM
R(eq) = Equivalent Resistor
R(eq)
VCC
EQUIVALENT OF EACH INPUT
VCC
Input
960
NOM
VCC
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal
10 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, V
I
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Notes 2 and 3): D package
97
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package
85
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS package
95
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, T
J
150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. Maximum power dissipation is a function of TJ(max),
JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) TA)/
JA. Operating at the absolute maximum TJ of 150
C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D JULY 1985 REVISED APRIL 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
TYP
MAX
UNIT
VCC
Supply voltage
4.75
5
5.25
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
12
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
7
V
VIH
High-level input voltage
D, DE, and RE
2
V
VIL
Low-level input voltage
D, DE, and RE
0.8
V
VID
Differential input voltage (see Note 4)
12
V
IOH
High level output current
Driver
60
mA
IOH
High-level output current
Receiver
400
A
IOL
Low level output current
Driver
60
mA
IOL
Low-level output current
Receiver
8
mA
TA
Operating free air temperature
SN65176B
40
105
C
TA
Operating free-air temperature
SN75176B
0
70
C
NOTE 4:
Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D JULY 1985 REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Input clamp voltage
II = 18 mA
1.5
V
VO
Output voltage
IO = 0
0
6
V
|VOD1|
Differential output voltage
IO = 0
1.5
3.6
6
V
|VOD2|
Differential output voltage
RL = 100
,
See Figure 1
1/2 VOD1
or 2
V
OD2
g
RL = 54
,
See Figure 1
1.5
2.5
5
VOD3
Differential output voltage
See Note 5
1.5
5
V
|VOD|
Change in magnitude
RL = 54
or 100
See Figure 1
0 2
V
|VOD|
g
g
of differential output voltage
RL = 54
or 100
,
See Figure 1
0.2
V
VOC
Common mode output voltage
RL = 54
or 100
See Figure 1
+3
V
VOC
Common-mode output voltage
RL = 54
or 100
,
See Figure 1
1
V
|VOC|
Change in magnitude
RL = 54
or 100
See Figure 1
0 2
V
|VOC|
g
g
of common-modeoutput voltage
RL = 54
or 100
,
See Figure 1
0.2
V
IO
Output current
Output disabled,
VO = 12 V
1
mA
IO
Output current
,
See Note 6
VO = 7 V
0.8
mA
IIH
High-level input current
VI = 2.4 V
20
A
IIL
Low-level input current
VI = 0.4 V
400
A
VO = 7 V
250
IOS
Short circuit output current
VO = 0
150
mA
IOS
Short-circuit output current
VO = VCC
250
mA
VO = 12 V
250
ICC
Supply current (total package)
No load
Outputs enabled
42
70
mA
ICC
Supply current (total package)
No load
Outputs disabled
26
35
mA
The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
All typical values are at VCC = 5 V and TA = 25
C.
|VOD| and
|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
The minimum VOD2 with a 100-
load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTES:
5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.
switching characteristics, V
CC
= 5 V, R
L
= 110
, T
A
= 25
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(OD)
Differential-output delay time
RL = 54
,
See Figure 3
15
22
ns
tt(OD)
Differential-output transition time
RL = 54
,
See Figure 3
20
30
ns
tPZH
Output enable time to high level
See Figure 4
85
120
ns
tPZL
Output enable time to low level
See Figure 5
40
60
ns
tPHZ
Output disable time from high level
See Figure 4
150
250
ns
tPLZ
Output disable time from low level
See Figure 5
20
30
ns
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