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FEATURES
APPLICATIONS
DESCRIPTION
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
D or P PACKAGE
(TOP VIEW)
LOGIC DIAGRAM (Positive Logic)
D
A
DE
RE
R
B
Host
SN65HVD08
Power Bus and Return Resistance
Isolation
Barrier
Remote
(One of n Shown)
5 V Power
Direct
Connection
to Host
5 V Return
SN75HVD08, SN65HVD08
SLLS550A NOVEMBER 2002 REVISED MAY 2003
WIDE SUPPLY RANGE RS-485 TRANSCEIVER
The wide supply voltage range and low quiescent
current requirements allow the SN65HVD08s to
Operates With a 3-V to 5.5-V Supply
operate from a 5-V power bus in the cable with as
Consumes Less Than 90 mW Quiescent
much as a 2-V line voltage drop. Busing power in the
Power
cable can alleviate the need for isolated power to be
generated at each connection of a ground-isolated
Open-Circuit, Short Circuit, and Idle-Bus
bus.
Failsafe Receiver
1/8
th
Unit-Load (up to 256 nodes on the bus)
The driver differential outputs and receiver differential
inputs connect internally to form a differential in-
Bus-Pin ESD Protection Exceeds 16 kV HBM
put/output (I/O) bus port that is designed to offer
Driver Output Voltage Slew-Rate Limited for
minimum loading to the bus whenever the driver is
Optimum Signal Quality at 10 Mbps
disabled or not powered. The drivers and receivers
Electrically Compatible With ANSI TIA/EIA-485
have active-high and active-low enables respectively,
which can be externally connected together to func-
Standard
tion as a direction control.
Data Transmission With Remote Stations
Powered From the Host
Isolated Multipoint Data Buses
Industrial Process Control Networks
Point-of-Sale Networks
Electric Utility Metering
The SN65HVD08 combines a 3-state differential line
driver and differential line receiver designed for bal-
anced data transmission and interoperation with ANSI
TIA/EIA-485-A and ISO-8482E standard-compliant
devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20022003, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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PACKAGE DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
SN75HVD08, SN65HVD08
SLLS550A NOVEMBER 2002 REVISED MAY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
SPECIFIED TEMPERATURE
PART NUMBER
PACKAGE
PACKAGE MARKING
RANGE
SN65HVD08D
40
C to 85
C
SOIC
VP08
SN65HVD08P
40
C to 85
C
PDIP
65HVD08
SN75HVD08D
0
C to 70
C
SOIC
VN08
SN75HVD08P
0
C to 70
C
PDIP
75HVD08
PACKAGE
T
A
25
C POWER RATING
DERATING FACTOR ABOVE T
A
= 25
C
T
A
= 85
C POWER RATING
SOIC (D)
710 mW
5.7 mW/
C
369 mW
PDIP (P)
1000 mW
8 mW/
C
520 mW
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
Supply voltage, V
CC
-0.3 V to 6 V
Voltage range at A or B
-9 V to 14 V
Input voltage range at D, DE, R or RE
-0.5 V to V
CC
+ 0.5 V
Voltage input range, transient pulse, A and B, through 100
-25 V to 25 V
A, B, and GND
16 kV
Human Body Model
(3)
Electrostatic discharge
All pins
4 kV
Charged-Device Model
(4)
All pins
1 kV
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature, T
stg
-65
C to 150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3)
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN
NOM
MAX
UNIT
Supply voltage, V
CC
3
5.5
V
Input voltage at any bus terminal (separately or common mode), V
I
(1)
7
12
V
High-level input voltage, V
IH
2.25
V
CC
Driver, driver enable, and receiver enable inputs
V
Low-level input voltage, V
IL
0
0.8
Differential input voltage, V
ID
12
12
Driver
60
High-level output current, I
OH
mA
Receiver
8
Driver
60
Low-level output current, I
OL
mA
Receiver
8
SN75HVD08
0
70
Operating free-air temperature, T
A
C
SN65HVD08
40
85
(1)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
2
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ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN75HVD08, SN65HVD08
SLLS550A NOVEMBER 2002 REVISED MAY 2003
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
L
= 60
, 375
on each output to
|V
OD
|
Driver differential output voltage magnitude
1.5
V
CC
V
-7 V to 12 V, See Figure 1
Change in magnitude of driver differential
|V
OD
|
R
L
= 54
0.2
0.2
V
output voltage
Peak-to-peak driver common-mode output
Center of two 27-
load
V
OC(PP)
0.5
V
voltage
resistors, See Figure 2
Positive-going receiver differential input volt-
V
IT+
10
mV
age threshold
Negative-going receiver differential input volt-
V
IT-
200
mV
age threshold
Receiver differential input voltage threshold
V
hys
35
mV
hysteresis(V
IT+
- V
IT-
)
V
OH
Receiver high-level output voltage
I
OH
= -8 mA
2.4
V
V
OL
Receiver low-level output voltage
I
OL
= 8 mA
0.4
V
Driver input, driver enable, and receiver en-
I
IH
100
100
A
able high-level input current
Driver input, driver enable, and receiver en-
I
IL
100
100
A
able low-level input current
I
OS
Driver short-circuit output current
7 V < V
O
< 12 V
265
265
mA
V
I
= 12 V
130
V
I
= -7 V
100
I
I
Bus input current (disabled driver)
A
V
I
= 12 V, V
CC
= 0 V
130
V
I
= -7 V. V
CC
= 0 V
100
Receiver enabled, driver
10
disabled, no load
mA
Driver enabled, receiver
16
I
CC
Supply current
disabled, no load
Both disabled
5
A
Both enabled, no load
16
mA
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PHL
Driver high-to-low propagation delay time
18
40
t
PLH
Driver low-to-high propagation delay time
18
40
t
r
Driver 10%-to-90% differential output rise time
R
L
= 54
, C
L
= 50 pF,See Figure 3
10
55
ns
t
f
Driver 90%-to-10% differential output fall time
10
55
t
SK(P)
Driver differential output pulse skew, |t
PHL
- t
PLH
|
2.5
Receiver enabled, See Figures 4 and 5
55
ns
t
en
Driver enable time
Receiver disabled, See Figures 4 and 5
6
s
t
dis
Driver disable time
Receiver enabled, See Figures 4 and 5
90
ns
3
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RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
60
1%
V
OD
0 or 3 V
_
+
7 V < V
(test)
< 12 V
DE
V
CC
A
B
D
375
1%
375
1%
V
OC
27
1%
Input
A
B
V
A
V
B
V
OC(PP)
V
OC(SS)
V
OC
27
1%
C
L
= 50 pF
20%
D
A
B
DE
V
CC
Input: PRR = 500 kHz, 50% Duty Cycle,t
r
<6ns, t
f
<6ns, Z
O
= 50
C
L
Includes Fixture and
Instrumentation Capacitance
V
OD
R
L
= 54
1%
50
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50
t
PLH
t
PHL
1.5 V
1.5 V
3 V
2 V
2 V
90%
10%
0 V
V
I
V
OD
t
r
t
f
C
L
= 50 pF
20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
CC
V
I
Input
Generator
90%
0 V
10%
SN75HVD08, SN65HVD08
SLLS550A NOVEMBER 2002 REVISED MAY 2003
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PHL
Receiver high-to-low propagation delay time
70
t
PLH
Receiver low-to-high propagation delay time
70
t
r
Receiver 10%-to-90% differential output rise time
C
L
= 15 pF, See Figure 6
5
ns
t
f
Receiver 90%-to-10% differential output fall time
5
t
SK(P)
Receiver differential output pulse skew, |t
PHL
- t
PLH
|
4.5
Driver enabled, See Figure 7
15
ns
t
en
Receiver enable time
Driver disabled, See Figure 8
6
s
t
dis
Receiver disable time
Driver enabled, See Figure 7
20
ns
Figure 1. Driver V
OD
With Common-Mode Loading Test Circuit
Figure 2. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 3. Driver Switching Test Circuit and Voltage Waveforms
4
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R
L
= 110
1%
Input
Generator
50
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50
3 V
S1
0.5 V
3 V
0 V
V
OH
0 V
t
PHZ
t
PZH
1.5 V
1.5 V
V
I
V
O
C
L
= 50 pF
20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
O
V
I
2.3 V
Input
Generator
50
3 V
V
O
S1
3 V
1.5 V
1.5 V
t
PZL
t
PLZ
2.3 V
0.5 V
3 V
0 V
V
OL
V
I
V
O
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50
R
L
= 110
1%
C
L
= 50 pF
20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
I
3 V
Input
Generator
50
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50
V
O
1.5 V
0 V
1.5 V
1.5 V
3 V
V
OH
V
OL
1.5 V
10%
1.5 V
t
PLH
t
PHL
t
r
t
f
90%
V
I
V
O
C
L
= 15 pF
20%
C
L
Includes Fixture
and Instrumentation
Capacitance
A
B
RE
V
I
R
0 V
90%
10%
SN75HVD08, SN65HVD08
SLLS550A NOVEMBER 2002 REVISED MAY 2003
Parameter Measurement Information (continued)
Figure 4. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 5. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 6. Receiver Switching Test Circuit and Voltage Waveforms
5
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