SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505F - FEBRUARY 2002 - REVISED NOVEMBER 2003
3.3 V RS 485 TRANSCEIVERS
FEATURES
D
Operates With a 3.3-V Supply
D
Bus-Pin ESD Protection Exceeds 16 kV HBM
D
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
D
Optional Driver Output Transition Times for
Signaling Rates
of 1 Mbps, 10 Mbps and
25 Mbps
D
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
D
Bus-Pin Short Circuit Protection From 7 V to
12 V
D
Low-Current Standby Mode . . . 1
A Typical
D
Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
D
Thermal Shutdown Protection
D
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
D
SN75176 Footprint
APPLICATIONS
D
Digital Motor Control
D
Utility Meters
D
Chassis-to-Chassis Interconnects
D
Electronic Security Stations
D
Industrial Process Control
D
Building Automation
D
Point-of-Sale (POS) Terminals and Networks
DESCRIPTION
The SN65HVD10, SN75HVD10, SN65HVD11,
SN75HVD11, SN65HVD12, and SN75HVD12 combine a
3-state differential line driver and differential input line
receiver that operate with a single 3.3-V power supply.
They are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and ISO
8482:1993. These differential bus transceivers are
monolithic integrated circuits designed for bidirectional
data communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and active-low
enables respectively, that can be externally connected
together to function as direction control. Very low device
standby supply current can be achieved by disabling the
driver and the receiver.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/ output
(I/O) bus port that is designed to offer minimum loading to
the bus whenever the driver is disabled or V
CC
= 0. These
parts feature wide positive and negative common-mode
voltage ranges, making them suitable for party-line
applications.
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
3
4
6
7
A
B
R
RE
DE
D
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2002-2003, Texas Instruments Incorporated
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505F - FEBRUARY 2002 - REVISED NOVEMBER 2003
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
SIGNALING RATE
UNIT LOADS
TA
PACKAGE
SOIC MARKING
SIGNALING RATE
UNIT LOADS
TA
SOIC(1)
PDIP
SOIC MARKING
25 Mbps
1/2
SN65HVD10D
SN65HVD10P
VP10
10 Mbps
1/8
-40
C to 85
C
SN65HVD11D
SN65HVD11P
VP11
1 Mbps
1/8
-40 C to 85 C
SN65HVD12D
SN65HVD12P
VP12
25 Mbps
1/2
SN75HVD10D
SN75HVD10P
VN10
10 Mbps
1/8
-0
C to 70
C
SN75HVD11D
SN75HVD11P
VN11
1 Mbps
1/8
-0 C to 70 C
SN75HVD12D
SN75HVD12P
VN12
25 Mbps
1/2
-40
C to 125
C
SN65HVD10QD
SN65HVD10QP
VP10Q
10 Mbps
1/8
-40
C to 125
C
SN65HVD11QD
SN65HVD11QP
VP11Q
(1) The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
SN65HVD10, SN75HVD10
SN65HVD11, SN75HVD11
SN65HVD12, SN75HVD12
Supply voltage range, VCC
-0.3 V to 6 V
Voltage range at A or B
-9 V to 14 V
Input voltage range at D, DE, R or RE
-0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100
(see Figure 11)
-50 V to 50 V
Human body model(3)
A, B and GND
16 kV
Electrostatic discharge
Human body model(3)
All pins
4 kV
Electrostatic discharge
Charged-device model(4)
All pins Charge
1 kV
Continuous total power dissipation
See Dissipation Rating Table
Junction temperature, TJ
170
C
Storage temperature range, Tstg
-65
C to 150
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
TA = 125
C
POWER RATING
D(2)
597 mW
4.97 mW/
C
373 mW
298 mW
100 mW
D(3)
990 mW
8.26 mW/
C
620 mW
496 mW
165 mW
P
1290 mW
10.75 mW/
C
806 mW
645 mW
215 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505F - FEBRUARY 2002 - REVISED NOVEMBER 2003
www.ti.com
3
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.6
V
Voltage at any bus terminal (separately or common mode) VI or VIC
-7(1)
12
V
High-level input voltage, VIH
D, DE, RE
2
VCC
V
Low-level input voltage, VIL
D, DE, RE
0
0.8
V
Differential input voltage, VID (see Figure 7)
-12
12
V
High-level output current, IOH
Driver
-60
mA
High-level output current, IOH
Receiver
-8
mA
Low-level output current, IOL
Driver
60
mA
Low-level output current, IOL
Receiver
8
mA
Differential load resistance, RL
54
60
Differential load capacitance, CL
50
pF
HVD10
25
Signaling rate
HVD11
10
Mbps
Signaling rate
HVD12
1
Mbps
Junction temperature, TJ(2)
145
C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIK
Input clamp voltage
II = -18 mA
-1.5
V
(2)
IO = 0
2
VCC
|VOD|
Differential output voltage(2)
RL = 54
, See Figure 1
1.5
V
|VOD|
Differential output voltage(2)
Vtest = -7 V to 12 V, See Figure 2
1.5
V
|VOD|
Change in magnitude of differential output
voltage
See Figure 1 and Figure 2
-0.2
0.2
V
VOC(PP)
Peak-to-peak common-mode output voltage
400
mV
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
1.4
2.5
V
VOC(SS)
Change in steady-state common-mode output
voltage
See Figure 3
-0.05
0.05
V
IOZ
High-impedance output current
See receiver input currents
II
Input current
D
-100
0
A
II
Input current
DE
0
100
A
IOS
Short-circuit output current
-7 V
VO
12 V
-250
250
mA
C(OD)
Differential output capacitance
VOD = 0.4 sin (4E6
t) + 0.5 V, DE at 0 V
16
pF
RE at VCC,
D & DE at
VCC, No load
Receiver disabled and
driver enabled
9
15.5
mA
ICC
Supply current
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and
driver disabled (standby)
1
5
A
RE at 0 V,
D & DE at
VCC, No load
Receiver enabled and
driver enabled
9
15.5
mA
(1) All typical values are at 25
C and with a 3.3-V supply.
(2) For TA > 85
C, VCC is
5%.
SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505F - FEBRUARY 2002 - REVISED NOVEMBER 2003
www.ti.com
4
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
HVD10
5
8.5
16
tPLH
Propagation delay time, low-to-high-level output
HVD11
18
25
40
ns
tPLH
Propagation delay time, low-to-high-level output
HVD12
135
200
300
ns
HVD10
5
8.5
16
tPHL
Propagation delay time, high-to-low-level output
HVD11
18
25
40
ns
tPHL
Propagation delay time, high-to-low-level output
HVD12
135
200
300
ns
HVD10
RL = 54
, CL = 50 pF,
3
4.5
10
tr
Differential output signal rise time
HVD11
RL = 54
, CL = 50 pF,
See Figure 4
10
20
30
ns
tr
Differential output signal rise time
HVD12
See Figure 4
100
170
300
ns
HVD10
3
4.5
10
tf
Differential output signal fall time
HVD11
10
20
30
ns
tf
Differential output signal fall time
HVD12
100
170
300
ns
HVD10
1.5
tsk(p)
Pulse skew (|tPHL - tPLH|)
HVD11
2.5
ns
tsk(p)
Pulse skew (|tPHL - tPLH|)
HVD12
7
ns
(2)
HVD10
6
tsk(pp)(2)
Part-to-part skew
HVD11
11
ns
tsk(pp)(2)
Part-to-part skew
HVD12
100
ns
Propagation delay time,
HVD10
31
tPZH
Propagation delay time,
high-impedance-to-high-level output
HVD11
55
ns
tPZH
high-impedance-to-high-level output
HVD12
RL = 110
,
RE at 0 V,
300
ns
Propagation delay time,
HVD10
RL = 110
,
RE at 0 V,
See Figure 5
25
tPHZ
Propagation delay time,
high-level-to-high-impedance output
HVD11
See Figure 5
55
ns
tPHZ
high-level-to-high-impedance output
HVD12
300
ns
Propagation delay time,
HVD10
26
tPZL
Propagation delay time,
high-impedance-to-low-level output
HVD11
55
ns
tPZL
high-impedance-to-low-level output
HVD12
RL = 110
,
RE at 0 V,
300
ns
Propagation delay time,
HVD10
RL = 110
,
RE at 0 V,
See Figure 6
26
tPLZ
Propagation delay time,
low-level-to-high-impedance output
HVD11
See Figure 6
75
ns
tPLZ
low-level-to-high-impedance output
HVD12
400
ns
tPZH
Propagation delay time, standby-to-high-level output
RL = 110
,
RE at 3 V,
See Figure 5
6
s
tPZL
Propagation delay time, standby-to-low-level output
RL = 110
,
RE at 3 V,
See Figure 6
6
s
(1) All typical values are at 25
C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
SN65HVD10,SN65HVD10Q,SN75HVD10
SN65HVD11,SN65HVD11Q,SN75HVD11
SN65HVD12,SN75HVD12
SLLS505F - FEBRUARY 2002 - REVISED NOVEMBER 2003
www.ti.com
5
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIT+
Positive-going input threshold voltage
IO = -8 mA
-0.01
VIT-
Negative-going input threshold
voltage
IO = 8 mA
-0.2
V
Vhys
Hysteresis voltage (VIT+ - VIT-)
35
mV
VIK
Enable-input clamp voltage
II = -18 mA
-1.5
V
VOH
High-level output voltage
VID = 200 mV,
IOH = -8 mA,
See Figure 7
2.4
V
VOL
Low-level output voltage
VID = -200 mV,
IOL = 8 mA,
See Figure 7
0.4
V
IOZ
High-impedance-state output current
VO = 0 or VCC
RE at VCC
-1
1
A
VA or VB = 12 V
0.05
0.11
VA or VB = 12 V,
VCC = 0 V
HVD11, HVD12,
0.06
0.13
mA
VA or VB = -7 V
HVD11, HVD12,
Other input at 0 V
-0.1
-0.05
mA
II
Bus input current
VA or VB = -7 V,
VCC = 0 V
Other input at 0 V
-0.05
-0.04
II
Bus input current
VA or VB = 12 V
0.2
0.5
VA or VB = 12 V,
VCC = 0 V
HVD10,
0.25
0.5
mA
VA or VB = -7 V
HVD10,
Other input at 0 V
-0.4
-0.2
mA
VA or VB = -7 V,
VCC = 0 V
Other input at 0 V
-0.4
-0.15
IIH
High-level input current, RE
VIH = 2 V
-30
0
A
IIL
Low-level input current, RE
VIL = 0.8 V
-30
0
A
CID
Differential input capacitance
VID = 0.4 sin (4E6
t) + 0.5 V, DE at 0 V
15
pF
RE at 0 V,
D & DE at 0 V,
No load
Receiver enabled and driver
disabled
4
8
mA
ICC
Supply current
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and driver
disabled (standby)
1
5
A
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled and driver
enabled
9
15.5
mA
(1) All typical values are at 25
C and with a 3.3-V supply.
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